From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 17:55:23 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~186
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=549d6ea467bddba24cc0ee43597b5ab62eb476e7;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

549d6ea467bddba24cc0ee43597b5ab62eb476e7
diff --cc passes/techmap/techmap.cc
index c2dc9b959,0c57733d4..a07a2f280
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@@ -256,15 -256,13 +256,21 @@@ struct TechmapWorke
  				if (w->attributes.count(ID(src)))
  					w->add_strpool_attribute(ID(src), extra_src_attrs);
  			}
 +
 +
 +			if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) {
 +				IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
 +				Wire *replace_w = module->addWire(replace_name, it.second);
 +				module->connect(replace_w, w);
 +			}
 +
  			design->select(module, w);
+ 
+ 			if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
+ 				IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
+ 				Wire *replace_w = module->addWire(replace_name, it.second);
+ 				module->connect(replace_w, w);
+ 			}
  		}
  
  		SigMap tpl_sigmap(tpl);