From: Luke Kenneth Casson Leighton Date: Sun, 6 Dec 2020 14:07:31 +0000 (+0000) Subject: add NLnet rfp tasks pending submission X-Git-Tag: convert-csv-opcode-to-binary~1498 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=549dee46870d9796b20eb4e02b10819db03337b2;p=libreriscv.git add NLnet rfp tasks pending submission --- diff --git a/lkcl.mdwn b/lkcl.mdwn index b0853355c..783779fab 100644 --- a/lkcl.mdwn +++ b/lkcl.mdwn @@ -12,7 +12,6 @@ move things along from one stage to the next ## Currently working on - Project Management - - LDST Dep Matrix (check if already RFPd) - ISAMux writeup - HDL changes for coriolis2 - @@ -36,26 +35,53 @@ move things along from one stage to the next - RA=0 tests - misc opcodes - FU multiple tasks - - Branch proof - - EUR 400 shared 25% [[mnolan]] EUR 100 - - ALU proof - - EUR 500 shared [[mnolan]] samuel, TBD split - mul bug - LD/ST cache-inhibit - EUR 200 - - DMI to JTAG - - EUR 250 (share with cole) - litex peripheral set - - pin-package for 180nm ASIC - ls180 reset review - JTAG boot upload/init - JTAG IO Boundary test - data handling API + - Formal proof of decoder + - donated + - parent #198 + - EUR 200 + - parent #197 + - MultiCompUnit (and Function Units) proof + - POWER9 ROTATE proof + - donated + - parent #195 ## Completed but not yet submitted: + - ULX3S boot + - Project 2019-10-043 06dec2020 wishbone + - EUR 0 (TBD) + +### Project 2019-10-029 14mar2020 coriolis2 + + - pin-package for 180nm ASIC + - (total EUR 100 shared 50% with staf) + - EUR 50 lkcl + - ls180 ioring and pads + - (total EUR 1500 shared 50% with LIP6) + - EUR 750 lkcl + - multi-clock example + - (total EUR 400 shared 75% with LIP6) + - EUR 300 lkcl + +### Project 2019-02-012 06dec2020 Core + - pipeline API continued - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200 + - CORDIC + - EUR 750 donated + - LDST Dep Matrix + - EUR 1500 + +### Project 2019-10-043 06dec2020 wishbone + - SPR pipe - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300 - DEC/TB @@ -72,31 +98,25 @@ move things along from one stage to the next - EUR 450 - addme bug - EUR 100 - - ULX3S boot - -donated: - - POWER Decoder - - with [[lkcl]] - - CORDIC - - - - functions needed for simulator - - Shared 90% with [[lkcl]] - - parent #198 - - Formal proof of decoder - - EUR 200 - - parent #195 - - POWER9 ALU proof - - parent #195 - - POWER9 CR proof - - parent #195 - - POWER9 BRANCH proof - - parent #195 - - POWER9 LOGICAL proof - - parent #195 - - POWER9 ROTATE proof - - parent #197 - - MultiCompUnit (and Function Units) proof + - EUR 200 donated + - DMI to JTAG + - EUR 250 (share with cole) + +### Project 2019-10-032 06dec2020 proofs + + - POWER9 ALU proof + - parent #195 + - EUR 400 donated + - POWER9 CR proof + - parent #195 + - EUR 300 donated + - POWER9 BRANCH proof + - EUR 400 donated + - parent #195 + - POWER9 LOGICAL proof + - EUR 400 donated + - parent #195 ## Submitted for NLNet RFP @@ -122,7 +142,7 @@ donation from NLNet confirmed received: - EUR 250, functions needed for simulator - Shared 20% with [[mnolan]], EUR 50 -#### proofs 2019-10-032 +### proofs 2019-10-032 - Trap proof - EUR 500 shared 20% samuel, EUR 100 @@ -199,7 +219,8 @@ donation from NLNet confirmed received: ### Project 2019-10-029 Date 14mar2020 -* coriolis2 start/tutorial EUR 1200 +* coriolis2 start/tutorial + - EUR 1200 ### Project 2019-02-012 Date 12mar2020