From: Julia Koval Date: Fri, 15 Dec 2017 05:04:33 +0000 (+0100) Subject: Enable VAES support [5/5] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=549fa5843dd13df696920b030f54eed1dcfbfe73;p=gcc.git Enable VAES support [5/5] gcc/ * config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi, __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New. * config/i386/sse.md (vaesenclast_): New pattern. * config/i386/vaesintrin.h (_mm256_aesenclast_epi128, _mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics. gcc/testsuite/ * gcc.target/i386/avx512f-aesenclast-2.c: New test. * gcc.target/i386/avx512vl-aesenclast-2.c: Ditto. * gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics. From-SVN: r255676 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6208c9ac333..453aa70025c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-12-15 Julia Koval + + * config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi, + __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New. + * config/i386/sse.md (vaesenclast_): New pattern. + * config/i386/vaesintrin.h (_mm256_aesenclast_epi128, + _mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics. + 2017-12-15 Julia Koval * config/i386/i386-builtin.def (__builtin_ia32_vaesenc_v16qi, diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 1fe9bdf6713..e3b12bdc318 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2773,6 +2773,9 @@ BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdec BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC_END (ARGS2, SPECIAL_ARGS2) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ac3793912da..c1469f457f5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -177,6 +177,7 @@ UNSPEC_VAESDEC UNSPEC_VAESDECLAST UNSPEC_VAESENC + UNSPEC_VAESENCLAST ]) (define_c_enum "unspecv" [ @@ -20487,3 +20488,13 @@ "TARGET_VAES" "vaesenc\t{%2, %1, %0|%0, %1, %2}" ) + +(define_insn "vaesenclast_" + [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") + (unspec:VI1_AVX512VL_F + [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") + (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] + UNSPEC_VAESENCLAST))] + "TARGET_VAES" + "vaesenclast\t{%2, %1, %0|%0, %1, %2}" +) diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h index 3bbfb391809..510a36edebf 100644 --- a/gcc/config/i386/vaesintrin.h +++ b/gcc/config/i386/vaesintrin.h @@ -29,6 +29,14 @@ _mm256_aesenc_epi128 (__m256i __A, __m256i __B) return (__m256i)__builtin_ia32_vaesenc_v32qi ((__v32qi) __A, (__v32qi) __B); } +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_aesenclast_epi128 (__m256i __A, __m256i __B) +{ + return (__m256i)__builtin_ia32_vaesenclast_v32qi ((__v32qi) __A, + (__v32qi) __B); +} + #ifdef __DISABLE_VAES__ #undef __DISABLE_VAES__ #pragma GCC pop_options @@ -64,6 +72,14 @@ _mm512_aesenc_epi128 (__m512i __A, __m512i __B) return (__m512i)__builtin_ia32_vaesenc_v64qi ((__v64qi) __A, (__v64qi) __B); } +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_aesenclast_epi128 (__m512i __A, __m512i __B) +{ + return (__m512i)__builtin_ia32_vaesenclast_v64qi ((__v64qi) __A, + (__v64qi) __B); +} + #ifdef __DISABLE_VAESF__ #undef __DISABLE_VAESF__ #pragma GCC pop_options @@ -97,6 +113,14 @@ _mm_aesenc_epi128 (__m128i __A, __m128i __B) return (__m128i)__builtin_ia32_vaesenc_v16qi ((__v16qi) __A, (__v16qi) __B); } +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_aesenclast_epi128 (__m128i __A, __m128i __B) +{ + return (__m128i)__builtin_ia32_vaesenclast_v16qi ((__v16qi) __A, + (__v16qi) __B); +} + #ifdef __DISABLE_VAESVL__ #undef __DISABLE_VAESVL__ #pragma GCC pop_options diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a38e6b5a916..a2992686bd6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-12-15 Julia Koval + + * gcc.target/i386/avx512f-aesenclast-2.c: New test. + * gcc.target/i386/avx512vl-aesenclast-2.c: Ditto. + * gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics. + 2017-12-15 Julia Koval * gcc.target/i386/avx512f-aesenc-2.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512f-aesenclast-2.c b/gcc/testsuite/gcc.target/i386/avx512f-aesenclast-2.c new file mode 100644 index 00000000000..03d333b57ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-aesenclast-2.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mvaes" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vaes } */ + +#define AVX512F + +#define VAES +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 32) + +#include "avx512f-mask-type.h" + +static void +CALC (unsigned int *r) +{ + for (int i = 0; i < SIZE; i+=4) + { + r[i] = 0xfbcda11; + r[i + 1] = 0x238dd93f; + r[i + 2] = 0x4adc62c0; + r[i + 3] = 0x3efbcb88; + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_ud) res1, src1, src2; + MASK_TYPE mask = MASK_VALUE; + unsigned int res_ref[SIZE]; + + for (int i = 0; i < SIZE; i+=4) + { + src1.a[i] = 0x5d53475d; + src1.a[i + 1] = 0x63746f72; + src1.a[i + 2] = 0x73745665; + src1.a[i + 3] = 0x7b5b5465; + src2.a[i] = 0x726f6e5d; + src2.a[i + 1] = 0x5b477565; + src2.a[i + 2] = 0x68617929; + src2.a[i + 3] = 0x48692853; + } + + CALC (res_ref); + res1.x = INTRINSIC (_aesenclast_epi128) (src2.x, src1.x); + + if (UNION_CHECK (AVX512F_LEN, i_ud) (res1, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c index 4a8f85ffe2c..19507a45e14 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c @@ -3,14 +3,17 @@ /* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vaesenclast\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vaesenclast\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vaesenclast\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -24,12 +27,15 @@ avx512f_test (void) x = _mm512_aesdec_epi128 (x, y); x = _mm512_aesdeclast_epi128 (x, y); x = _mm512_aesenc_epi128 (x, y); + x = _mm512_aesenclast_epi128 (x, y); x256 = _mm256_aesdec_epi128 (x256, y256); x256 = _mm256_aesdeclast_epi128 (x256, y256); x256 = _mm256_aesenc_epi128 (x256, y256); + x256 = _mm256_aesenclast_epi128 (x256, y256); x128 = _mm_aesdec_epi128 (x128, y128); x128 = _mm_aesdeclast_epi128 (x128, y128); x128 = _mm_aesenc_epi128 (x128, y128); + x128 = _mm_aesenclast_epi128 (x128, y128); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-aesenclast-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-aesenclast-2.c new file mode 100644 index 00000000000..0f78a6635a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-aesenclast-2.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mvaes" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512bw } */ +/* { dg-require-effective-target avx512vaes } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-aesenclast-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-aesenclast-2.c"