From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 Jun 2020 14:54:49 +0000 (+0100)
Subject: add in memory setup/check but disable LDST Unit Tests in core.py
X-Git-Tag: div_pipeline~374
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54a1dbf96e7092aebf59c76ec99aed678f861dae;p=soc.git

add in memory setup/check but disable LDST Unit Tests in core.py
LDST is still busy after 2nd instruction, bug needs tracking down
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 54014a00..8b633c7b 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -19,12 +19,16 @@ from soc.decoder.power_enums import Function, XER_bits
 from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok # hack
 
+from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+                                                 check_sim_memory)
+
 # test with ALU data and Logical data
 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 
 
 def set_issue(core, dec2, sim):
@@ -62,11 +66,17 @@ class TestRunner(FHDLTestCase):
         m.submodules.core = core = NonProductionCore()
         pdecode = core.pdecode
         pdecode2 = core.pdecode2
+        l0 = core.l0
 
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         comb += core.ivalid_i.eq(ivalid_i)
         sim = Simulator(m)
 
+        # temporary hack: says "go" immediately for both address gen and ST
+        ldst = core.fus.fus['ldst0']
+        m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
+        m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
+
         sim.add_clock(1e-6)
 
         def process():
@@ -82,6 +92,8 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
+                yield from setup_test_memory(l0, sim)
+
                 # set up INT regfile, "direct" write (bypass rd/write ports)
                 for i in range(32):
                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
@@ -202,6 +214,9 @@ class TestRunner(FHDLTestCase):
                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 
+                    # Memory check
+                    yield from check_sim_memory(self, l0, sim, code)
+
         sim.add_sync_process(process)
         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
                             traces=[]):
@@ -211,6 +226,7 @@ class TestRunner(FHDLTestCase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
+    #suite.addTest(TestRunner(LDSTTestCase.test_data))
     suite.addTest(TestRunner(CRTestCase.test_data))
     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     suite.addTest(TestRunner(LogicalTestCase.test_data))