From: lkcl <lkcl@web>
Date: Mon, 22 Feb 2021 04:15:37 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54c775dcba16e97c5e9480ca89ed0ba27c484b62;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 88ac14d47..20ad7d325 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -149,6 +149,8 @@ When Rc=1 is encountered in an SVP64 Context the destination is different (TODO)
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP svslar may also be adjusted.
+
 ## Single Predication
 
 TODO