From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Wed, 27 Oct 2021 11:14:34 +0000 (+0200)
Subject: dfflegalize: Add tests targetting aldff.
X-Git-Tag: yosys-0.11~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54c79af64f8c84b8a9d8c1be2be5a6862910c2bb;p=yosys.git

dfflegalize: Add tests targetting aldff.
---

diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys
index 135ae0ab7..fc579e7d6 100644
--- a/tests/techmap/dfflegalize_adff.ys
+++ b/tests/techmap/dfflegalize_adff.ys
@@ -39,6 +39,8 @@ design -save orig
 flatten
 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
 
@@ -73,6 +75,36 @@ select -assert-count 14 t:$_DFFE_PP0P_
 select -assert-none t:$_DFFE_PP0P_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys
index 27798ac52..25ed59307 100644
--- a/tests/techmap/dfflegalize_adff_init.ys
+++ b/tests/techmap/dfflegalize_adff_init.ys
@@ -45,6 +45,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
@@ -221,6 +225,60 @@ select -assert-count 4 adffe1/t:$_DLATCH_P_
 select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 10 adffe0/t:$_NOT_
+select -assert-count 10 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 11 adffe0/t:$_NOT_
+select -assert-count 11 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys
index 4022da5f4..374289678 100644
--- a/tests/techmap/dfflegalize_dff.ys
+++ b/tests/techmap/dfflegalize_dff.ys
@@ -70,6 +70,8 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
@@ -176,6 +178,56 @@ select -assert-count 27 t:$_DFFE_PP0P_
 select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys
index ccde4c324..a170249c7 100644
--- a/tests/techmap/dfflegalize_dff_init.ys
+++ b/tests/techmap/dfflegalize_dff_init.ys
@@ -78,6 +78,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
@@ -371,6 +375,100 @@ select -assert-count 27 t:$_DFFE_PP1P_
 select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys
index b68ea741e..11683bc1a 100644
--- a/tests/techmap/dfflegalize_dlatch.ys
+++ b/tests/techmap/dfflegalize_dlatch.ys
@@ -11,6 +11,8 @@ design -save orig
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 
 # Convert everything to DFFs.
 
@@ -40,3 +42,23 @@ dfflegalize -cell $_DLATCHSR_PPP_ x
 select -assert-count 1 t:$_NOT_
 select -assert-count 2 t:$_DLATCHSR_PPP_
 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys
index ccc9e41d7..9324c6691 100644
--- a/tests/techmap/dfflegalize_dlatch_init.ys
+++ b/tests/techmap/dfflegalize_dlatch_init.ys
@@ -16,6 +16,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 
 # Convert everything to DFFs.
 
@@ -80,3 +84,37 @@ dfflegalize -cell $_DLATCHSR_PPP_ 1
 select -assert-count 5 t:$_NOT_
 select -assert-count 2 t:$_DLATCHSR_PPP_
 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys
index cb42e01a8..a74d74161 100644
--- a/tests/techmap/dfflegalize_inv.ys
+++ b/tests/techmap/dfflegalize_inv.ys
@@ -2,7 +2,7 @@
 
 read_verilog -icells <<EOT
 
-module top(input C, E, R, S, D, output [64:0] Q);
+module top(input C, E, R, S, D, L, AD, output [71:0] Q);
 
 $_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
 $_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
@@ -88,16 +88,25 @@ $_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62]));
 $_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63]));
 $_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64]));
 
+$_ALDFF_PP_ ff65 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[65]));
+$_ALDFF_PN_ ff66 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[66]));
+$_ALDFF_NP_ ff67 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[67]));
+
+$_ALDFFE_PPP_ ff68 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[68]));
+$_ALDFFE_PPN_ ff69 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[69]));
+$_ALDFFE_PNP_ ff70 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[70]));
+$_ALDFFE_NPP_ ff71 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[71]));
+
 endmodule
 
 EOT
 
 design -save orig
 
-equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
 design -load postopt
 
-select -assert-count 46 t:$_NOT_
+select -assert-count 51 t:$_NOT_
 select -assert-count 2 t:$_DFF_P_
 select -assert-count 3 t:$_DFFE_PP_
 select -assert-count 3 t:$_DFF_PP0_
@@ -117,16 +126,18 @@ select -assert-count 3 t:$_DLATCH_PP0_
 select -assert-count 3 t:$_DLATCH_PP1_
 select -assert-count 4 t:$_DLATCHSR_PPP_
 select -assert-count 3 t:$_SR_PP_
-select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_NOT_ %% %n t:* %i
+select -assert-count 3 t:$_ALDFF_PP_
+select -assert-count 4 t:$_ALDFFE_PPP_
+select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_ALDFF_PP_ t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
 
 # Now try it again, targetting the opposite cells.
 
 design -load orig
 
-equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
 design -load postopt
 
-select -assert-count 122 t:$_NOT_
+select -assert-count 135 t:$_NOT_
 select -assert-count 2 t:$_DFF_N_
 select -assert-count 3 t:$_DFFE_NN_
 select -assert-count 3 t:$_DFF_NN0_
@@ -146,7 +157,9 @@ select -assert-count 3 t:$_DLATCH_NN0_
 select -assert-count 3 t:$_DLATCH_NN1_
 select -assert-count 4 t:$_DLATCHSR_NNN_
 select -assert-count 3 t:$_SR_NN_
-select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_NOT_ %% %n t:* %i
+select -assert-count 3 t:$_ALDFF_NN_
+select -assert-count 4 t:$_ALDFFE_NNN_
+select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_ALDFF_NN_ t:$_ALDFFE_NNN_ t:$_NOT_ %% %n t:* %i
 
 
 # Second test: make sure set/reset/enable are inverted before clock.