From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Mar 2019 07:56:37 +0000 (+0000)
Subject: connect up mids through modules
X-Git-Tag: ls180-24jan2020~1537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54c833673d6da2b0cf6a625ecaa6652719dc59e0;p=ieee754fpu.git

connect up mids through modules
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 46e9223f..6cd891dd 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -209,6 +209,7 @@ class FPGet2OpMod(Trigger):
                 out_op2.decode(self.i.b),
                 self.o.a.eq(out_op1),
                 self.o.b.eq(out_op2),
+                self.o.mid.eq(self.i.mid)
             ]
         return m
 
@@ -366,6 +367,8 @@ class FPAddSpecialCasesMod:
         with m.Else():
             m.d.comb += self.out_do_z.eq(0)
 
+        m.d.comb += self.o.mid.eq(self.i.mid)
+
         return m
 
 
@@ -401,7 +404,7 @@ class FPAddSpecialCases(FPState):
         """
         self.mod.setup(m, i, self.out_do_z)
         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
-        m.d.sync += self.out_z.mid.eq(self.pmod.o.mid)  # (and mid)
+        m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 
     def action(self, m):
         self.idsync(m)
@@ -484,6 +487,8 @@ class FPAddDeNormMod(FPState):
         with m.Else():
             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 
+        m.d.comb += self.o.mid.eq(self.i.mid)
+
         return m
 
 
@@ -669,6 +674,9 @@ class FPAddAlignSingleMod:
                          self.o.a.eq(t_out),
                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
                         ]
+
+        m.d.comb += self.o.mid.eq(self.i.mid)
+
         return m
 
 
@@ -767,6 +775,7 @@ class FPAddStage0Mod:
         m.submodules.add0_in_b = self.i.b
         m.submodules.add0_out_z = self.o.z
 
+        m.d.comb += self.o.mid.eq(self.i.mid)
         m.d.comb += self.o.z.e.eq(self.i.a.e)
 
         # store intermediate tests (and zero-extended mantissas)
@@ -867,6 +876,7 @@ class FPAddStage1Mod(FPState):
         #m.submodules.norm1_in_z = self.in_z
         #m.submodules.norm1_out_z = self.out_z
         m.d.comb += self.o.z.eq(self.i.z)
+        m.d.comb += self.o.mid.eq(self.i.mid)
         # tot[-1] (MSB) gets set when the sum overflows. shift result down
         with m.If(self.i.tot[-1]):
             m.d.comb += [