From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Sun, 13 Sep 2020 11:13:59 +0000 (+0100)
Subject: arch-x86: Replace any getDTBPtr/getITBPtr usage
X-Git-Tag: develop-gem5-snapshot~555
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55004009501785a11e6f39e42d01540f0999e704;p=gem5.git

arch-x86: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
---

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 36cc47e43..a50751510 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,6 +42,7 @@
 
 #include "arch/x86/generated/decoder.hh"
 #include "arch/x86/isa_traits.hh"
+#include "arch/x86/mmu.hh"
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
@@ -137,8 +138,7 @@ PageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     if (FullSystem) {
         // Invalidate any matching TLB entries before handling the page fault.
-        tc->getITBPtr()->demapPage(addr, 0);
-        tc->getDTBPtr()->demapPage(addr, 0);
+        tc->getMMUPtr()->demapPage(addr, 0);
         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
         X86FaultBase::invoke(tc);
         // If something bad happens while trying to enter the page fault
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1b2504abc..86182879a 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -29,7 +29,7 @@
 #include "arch/x86/isa.hh"
 
 #include "arch/x86/decoder.hh"
-#include "arch/x86/tlb.hh"
+#include "arch/x86/mmu.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "params/X86ISA.hh"
@@ -239,8 +239,7 @@ ISA::setMiscReg(int miscReg, RegVal val)
                 }
             }
             if (toggled.pg) {
-                dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
-                dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
+                tc->getMMUPtr()->flushAll();
             }
             //This must always be 1.
             newCR0.et = 1;
@@ -255,15 +254,13 @@ ISA::setMiscReg(int miscReg, RegVal val)
       case MISCREG_CR2:
         break;
       case MISCREG_CR3:
-        dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
-        dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
+        static_cast<MMU *>(tc->getMMUPtr())->flushNonGlobal();
         break;
       case MISCREG_CR4:
         {
             CR4 toggled = regVal[miscReg] ^ val;
             if (toggled.pae || toggled.pse || toggled.pge) {
-                dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
-                dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
+                tc->getMMUPtr()->flushAll();
             }
         }
         break;
diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh
index 4f3411a19..70afea3c3 100644
--- a/src/arch/x86/mmu.hh
+++ b/src/arch/x86/mmu.hh
@@ -39,6 +39,7 @@
 #define __ARCH_X86_MMU_HH__
 
 #include "arch/generic/mmu.hh"
+#include "arch/x86/tlb.hh"
 
 #include "params/X86MMU.hh"
 
@@ -50,6 +51,19 @@ class MMU : public BaseMMU
     MMU(const X86MMUParams &p)
       : BaseMMU(p)
     {}
+
+    void
+    flushNonGlobal()
+    {
+        static_cast<TLB*>(itb)->flushNonGlobal();
+        static_cast<TLB*>(dtb)->flushNonGlobal();
+    }
+
+    Walker*
+    getDataWalker()
+    {
+        return static_cast<TLB*>(dtb)->getWalker();
+    }
 };
 
 } // namespace X86ISA
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 9603b9069..2f38fd5f3 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -44,6 +44,7 @@
 
 #include <string>
 
+#include "arch/x86/mmu.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/process.hh"
 #include "arch/x86/regs/int.hh"
@@ -68,8 +69,8 @@ bool
 RemoteGDB::acc(Addr va, size_t len)
 {
     if (FullSystem) {
-        Walker *walker = dynamic_cast<TLB *>(
-            context()->getDTBPtr())->getWalker();
+        Walker *walker = dynamic_cast<MMU *>(
+            context()->getMMUPtr())->getDataWalker();
         unsigned logBytes;
         Fault fault = walker->startFunctional(context(), va, logBytes,
                                               BaseTLB::Read);
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b9371b5..7d891afb7 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -39,6 +39,7 @@
 #include "arch/x86/utility.hh"
 
 #include "arch/x86/interrupts.hh"
+#include "arch/x86/mmu.hh"
 #include "arch/x86/registers.hh"
 #include "arch/x86/x86_traits.hh"
 #include "cpu/base.hh"
@@ -86,8 +87,7 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
     // CPU switch have different frequencies.
     dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
 
-    dest->getITBPtr()->flushAll();
-    dest->getDTBPtr()->flushAll();
+    dest->getMMUPtr()->flushAll();
 }
 
 void