From: Florent Kermarrec Date: Mon, 16 Feb 2015 09:05:04 +0000 (+0100) Subject: move lm32/mor1kx submodules to extcores X-Git-Tag: 24jan2021_ls180~2609 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5500c419159a7e702e76c8abd4008e5a176965ec;p=litex.git move lm32/mor1kx submodules to extcores --- diff --git a/.gitmodules b/.gitmodules index a952646d..aa337e22 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,8 @@ -[submodule "verilog/lm32/submodule"] - path = verilog/lm32/submodule +[submodule "extcores/lm32/submodule"] + path = extcores/lm32/submodule url = https://github.com/m-labs/lm32.git -[submodule "verilog/mor1kx/submodule"] - path = verilog/mor1kx/submodule +[submodule "extcores/mor1kx/submodule"] + path = extcores/mor1kx/submodule url = https://github.com/openrisc/mor1kx.git [submodule "software/compiler-rt"] path = software/compiler-rt diff --git a/extcores/lm32/lm32_config.v b/extcores/lm32/lm32_config.v new file mode 100644 index 00000000..41c2daad --- /dev/null +++ b/extcores/lm32/lm32_config.v @@ -0,0 +1,199 @@ +`ifdef LM32_CONFIG_V +`else +`define LM32_CONFIG_V + +// +// EXCEPTION VECTORS BASE ADDRESS +// + +// Base address for exception vectors +`define CFG_EBA_RESET 32'h00000000 + +// Base address for the debug exception vectors. If the DC_RE flag is +// set or the at_debug signal is asserted (see CFG_ALTERNATE_EBA) this +// will also be used for normal exception vectors. +`define CFG_DEBA_RESET 32'h10000000 + +// Enable exception vector remapping by external signal +//`define CFG_ALTERNATE_EBA + + +// +// ALU OPTIONS +// + +// Enable sign-extension instructions +`define CFG_SIGN_EXTEND_ENABLED + +// Shifter +// You may either enable the piplined or the multi-cycle barrel +// shifter. The multi-cycle shifter will stall the pipeline until +// the result is available after 32 cycles. +// If both options are disabled, only "right shift by one bit" is +// available. +//`define CFG_MC_BARREL_SHIFT_ENABLED +`define CFG_PL_BARREL_SHIFT_ENABLED + +// Multiplier +// The multiplier is available either in a multi-cycle version or +// in a pipelined one. The multi-cycle multiplier stalls the pipe +// for 32 cycles. If both options are disabled, multiply operations +// are not supported. +//`define CFG_MC_MULTIPLY_ENABLED +`define CFG_PL_MULTIPLY_ENABLED + +// Enable the multi-cycle divider. Stalls the pipe until the result +// is ready after 32 cycles. If disabled, the divide operation is not +// supported. +`define CFG_MC_DIVIDE_ENABLED + + +// +// INTERRUPTS +// + +// Enable support for 32 hardware interrupts +`define CFG_INTERRUPTS_ENABLED + +// Enable level-sensitive interrupts. The interrupt line status is +// reflected in the IP register, which is then read-only. +`define CFG_LEVEL_SENSITIVE_INTERRUPTS + + +// +// USER INSTRUCTION +// + +// Enable support for the user opcode. +//`define CFG_USER_ENABLED + + +// +// MEMORY MANAGEMENT UNIT +// + +// Enable instruction and data translation lookaside buffers and +// restricted user mode. +//`define CFG_MMU_ENABLED + + +// +// CACHE +// + +// Instruction cache +`define CFG_ICACHE_ENABLED +`define CFG_ICACHE_ASSOCIATIVITY 1 +`define CFG_ICACHE_SETS 256 +`define CFG_ICACHE_BYTES_PER_LINE 16 +`define CFG_ICACHE_BASE_ADDRESS 32'h00000000 +`define CFG_ICACHE_LIMIT 32'h7fffffff + +// Data cache +`define CFG_DCACHE_ENABLED +`define CFG_DCACHE_ASSOCIATIVITY 1 +`define CFG_DCACHE_SETS 256 +`define CFG_DCACHE_BYTES_PER_LINE 16 +`define CFG_DCACHE_BASE_ADDRESS 32'h00000000 +`define CFG_DCACHE_LIMIT 32'h7fffffff + + +// +// DEBUG OPTION +// + +// Globally enable debugging +//`define CFG_DEBUG_ENABLED + +// Enable the hardware JTAG debugging interface. +// Note: to use this, there must be a special JTAG module for your +// device. At the moment, there is only support for the +// Spartan-6. +//`define CFG_JTAG_ENABLED + +// JTAG UART is a communication channel which uses JTAG to transmit +// and receive bytes to and from the host computer. +//`define CFG_JTAG_UART_ENABLED + +// Enable reading and writing to the memory and writing CSRs using +// the JTAG interface. +//`define CFG_HW_DEBUG_ENABLED + +// Number of hardware watchpoints, max. 4 +//`define CFG_WATCHPOINTS 32'h4 + +// Enable hardware breakpoints +//`define CFG_ROM_DEBUG_ENABLED + +// Number of hardware breakpoints, max. 4 +//`define CFG_BREAKPOINTS 32'h4 + +// Put the processor into debug mode by an external signal. That is, +// raise a breakpoint exception. This is useful if you have a debug +// monitor and a serial line and you want to trap into the monitor on a +// BREAK symbol on the serial line. +//`define CFG_EXTERNAL_BREAK_ENABLED + + +// +// REGISTER FILE +// + +// The following option explicitly infers block RAM for the register +// file. There is extra logic to avoid parallel writes and reads. +// Normally, if your synthesizer is smart enough, this should not be +// necessary because it will automatically infer block RAM for you. +//`define CFG_EBR_POSEDGE_REGISTER_FILE + +// Explicitly infers block RAM, too. But it uses two different clocks, +// one being shifted by 180deg, for the read and write port. Therefore, +// no additional logic to avoid the parallel write/reads. +//`define CFG_EBR_NEGEDGE_REGISTER_FILE + + +// +// MISCELLANEOUS +// + +// Exceptions on wishbone bus errors +//`define CFG_BUS_ERRORS_ENABLED + +// Enable the cycle counter +`define CFG_CYCLE_COUNTER_ENABLED + +// Embedded instruction ROM using on-chip block RAM +//`define CFG_IROM_ENABLED +//`define CFG_IROM_INIT_FILE "NONE" +//`define CFG_IROM_BASE_ADDRESS 32'h10000000 +//`define CFG_IROM_LIMIT 32'h10000fff + +// Embedded data RAM using on-chip block RAM +//`define CFG_DRAM_ENABLED +//`define CFG_DRAM_INIT_FILE "NONE" +//`define CFG_DRAM_BASE_ADDRESS 32'h20000000 +//`define CFG_DRAM_LIMIT 32'h20000fff + +// Trace unit +//`define CFG_TRACE_ENABLED + +// Resolve unconditional branches already in the X stage (UNTESTED!) +//`define CFG_FAST_UNCONDITIONAL_BRANCH + +// log2 function +// If your simulator/synthesizer does not support the $clog2 system +// function you can use a constant function instead. + +function integer clog2; + input integer value; + begin + value = value - 1; + for (clog2 = 0; value > 0; clog2 = clog2 + 1) + value = value >> 1; + end +endfunction + +`define CLOG2 clog2 + +//`define CLOG2 $clog2 + +`endif diff --git a/extcores/lm32/submodule b/extcores/lm32/submodule new file mode 160000 index 00000000..84b3e3ca --- /dev/null +++ b/extcores/lm32/submodule @@ -0,0 +1 @@ +Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08 diff --git a/extcores/mor1kx/submodule b/extcores/mor1kx/submodule new file mode 160000 index 00000000..95fc8e43 --- /dev/null +++ b/extcores/mor1kx/submodule @@ -0,0 +1 @@ +Subproject commit 95fc8e432d762e48b42991663cf9d0cdb918e27e diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index e07d9587..9d490ccf 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -75,15 +75,15 @@ class GenSoC(Module): # add CPU Verilog sources if cpu_type == "lm32": - platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), + platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join("verilog", "lm32")) + platform.add_verilog_include_path(os.path.join("extcores", "lm32")) if cpu_type == "or1k": - platform.add_source_dir(os.path.join("verilog", "mor1kx", "submodule", "rtl", "verilog")) + platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog")) def register_rom(self, rom_wb_if, bios_size=0xa000): if self._rom_registered: diff --git a/verilog/lm32/lm32_config.v b/verilog/lm32/lm32_config.v deleted file mode 100644 index 41c2daad..00000000 --- a/verilog/lm32/lm32_config.v +++ /dev/null @@ -1,199 +0,0 @@ -`ifdef LM32_CONFIG_V -`else -`define LM32_CONFIG_V - -// -// EXCEPTION VECTORS BASE ADDRESS -// - -// Base address for exception vectors -`define CFG_EBA_RESET 32'h00000000 - -// Base address for the debug exception vectors. If the DC_RE flag is -// set or the at_debug signal is asserted (see CFG_ALTERNATE_EBA) this -// will also be used for normal exception vectors. -`define CFG_DEBA_RESET 32'h10000000 - -// Enable exception vector remapping by external signal -//`define CFG_ALTERNATE_EBA - - -// -// ALU OPTIONS -// - -// Enable sign-extension instructions -`define CFG_SIGN_EXTEND_ENABLED - -// Shifter -// You may either enable the piplined or the multi-cycle barrel -// shifter. The multi-cycle shifter will stall the pipeline until -// the result is available after 32 cycles. -// If both options are disabled, only "right shift by one bit" is -// available. -//`define CFG_MC_BARREL_SHIFT_ENABLED -`define CFG_PL_BARREL_SHIFT_ENABLED - -// Multiplier -// The multiplier is available either in a multi-cycle version or -// in a pipelined one. The multi-cycle multiplier stalls the pipe -// for 32 cycles. If both options are disabled, multiply operations -// are not supported. -//`define CFG_MC_MULTIPLY_ENABLED -`define CFG_PL_MULTIPLY_ENABLED - -// Enable the multi-cycle divider. Stalls the pipe until the result -// is ready after 32 cycles. If disabled, the divide operation is not -// supported. -`define CFG_MC_DIVIDE_ENABLED - - -// -// INTERRUPTS -// - -// Enable support for 32 hardware interrupts -`define CFG_INTERRUPTS_ENABLED - -// Enable level-sensitive interrupts. The interrupt line status is -// reflected in the IP register, which is then read-only. -`define CFG_LEVEL_SENSITIVE_INTERRUPTS - - -// -// USER INSTRUCTION -// - -// Enable support for the user opcode. -//`define CFG_USER_ENABLED - - -// -// MEMORY MANAGEMENT UNIT -// - -// Enable instruction and data translation lookaside buffers and -// restricted user mode. -//`define CFG_MMU_ENABLED - - -// -// CACHE -// - -// Instruction cache -`define CFG_ICACHE_ENABLED -`define CFG_ICACHE_ASSOCIATIVITY 1 -`define CFG_ICACHE_SETS 256 -`define CFG_ICACHE_BYTES_PER_LINE 16 -`define CFG_ICACHE_BASE_ADDRESS 32'h00000000 -`define CFG_ICACHE_LIMIT 32'h7fffffff - -// Data cache -`define CFG_DCACHE_ENABLED -`define CFG_DCACHE_ASSOCIATIVITY 1 -`define CFG_DCACHE_SETS 256 -`define CFG_DCACHE_BYTES_PER_LINE 16 -`define CFG_DCACHE_BASE_ADDRESS 32'h00000000 -`define CFG_DCACHE_LIMIT 32'h7fffffff - - -// -// DEBUG OPTION -// - -// Globally enable debugging -//`define CFG_DEBUG_ENABLED - -// Enable the hardware JTAG debugging interface. -// Note: to use this, there must be a special JTAG module for your -// device. At the moment, there is only support for the -// Spartan-6. -//`define CFG_JTAG_ENABLED - -// JTAG UART is a communication channel which uses JTAG to transmit -// and receive bytes to and from the host computer. -//`define CFG_JTAG_UART_ENABLED - -// Enable reading and writing to the memory and writing CSRs using -// the JTAG interface. -//`define CFG_HW_DEBUG_ENABLED - -// Number of hardware watchpoints, max. 4 -//`define CFG_WATCHPOINTS 32'h4 - -// Enable hardware breakpoints -//`define CFG_ROM_DEBUG_ENABLED - -// Number of hardware breakpoints, max. 4 -//`define CFG_BREAKPOINTS 32'h4 - -// Put the processor into debug mode by an external signal. That is, -// raise a breakpoint exception. This is useful if you have a debug -// monitor and a serial line and you want to trap into the monitor on a -// BREAK symbol on the serial line. -//`define CFG_EXTERNAL_BREAK_ENABLED - - -// -// REGISTER FILE -// - -// The following option explicitly infers block RAM for the register -// file. There is extra logic to avoid parallel writes and reads. -// Normally, if your synthesizer is smart enough, this should not be -// necessary because it will automatically infer block RAM for you. -//`define CFG_EBR_POSEDGE_REGISTER_FILE - -// Explicitly infers block RAM, too. But it uses two different clocks, -// one being shifted by 180deg, for the read and write port. Therefore, -// no additional logic to avoid the parallel write/reads. -//`define CFG_EBR_NEGEDGE_REGISTER_FILE - - -// -// MISCELLANEOUS -// - -// Exceptions on wishbone bus errors -//`define CFG_BUS_ERRORS_ENABLED - -// Enable the cycle counter -`define CFG_CYCLE_COUNTER_ENABLED - -// Embedded instruction ROM using on-chip block RAM -//`define CFG_IROM_ENABLED -//`define CFG_IROM_INIT_FILE "NONE" -//`define CFG_IROM_BASE_ADDRESS 32'h10000000 -//`define CFG_IROM_LIMIT 32'h10000fff - -// Embedded data RAM using on-chip block RAM -//`define CFG_DRAM_ENABLED -//`define CFG_DRAM_INIT_FILE "NONE" -//`define CFG_DRAM_BASE_ADDRESS 32'h20000000 -//`define CFG_DRAM_LIMIT 32'h20000fff - -// Trace unit -//`define CFG_TRACE_ENABLED - -// Resolve unconditional branches already in the X stage (UNTESTED!) -//`define CFG_FAST_UNCONDITIONAL_BRANCH - -// log2 function -// If your simulator/synthesizer does not support the $clog2 system -// function you can use a constant function instead. - -function integer clog2; - input integer value; - begin - value = value - 1; - for (clog2 = 0; value > 0; clog2 = clog2 + 1) - value = value >> 1; - end -endfunction - -`define CLOG2 clog2 - -//`define CLOG2 $clog2 - -`endif diff --git a/verilog/lm32/submodule b/verilog/lm32/submodule deleted file mode 160000 index dfd6ca7b..00000000 --- a/verilog/lm32/submodule +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dfd6ca7bfc1cf0a6ff306cb95bcae62915091301 diff --git a/verilog/mor1kx/submodule b/verilog/mor1kx/submodule deleted file mode 160000 index 64651c8a..00000000 --- a/verilog/mor1kx/submodule +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 64651c8af488a498f059c54fcd9580b1d16ac6c4