From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 11:37:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5522
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=550811bace6ef3c342052dc0403853852b54cf38;p=libreriscv.git

---

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 06bb1aae6..f470b2868 100644
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -1,6 +1,6 @@
 # Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
 
-## Proposed vector instruction encoding
+## Proposed Harmonised RVP vector op instruction encoding
 
 Register x 2 -> register operations: