From: Luke Kenneth Casson Leighton Date: Mon, 5 Jul 2021 22:16:11 +0000 (+0100) Subject: add 2nd matrix multiply unit test with SV REMAP X-Git-Tag: xlen-bcd~340 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=550bf8916e8da65003bcd4ce88d69f4228649fdf;p=openpower-isa.git add 2nd matrix multiply unit test with SV REMAP --- diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py index 8fd5e5fd..edc9c2bb 100644 --- a/src/openpower/decoder/isa/test_caller.py +++ b/src/openpower/decoder/isa/test_caller.py @@ -45,6 +45,11 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, def process(): + print ("GPRs") + simulator.gpr.dump() + print ("FPRs") + simulator.fpr.dump() + yield pdecode2.dec.bigendian.eq(0) # little / big? pc = simulator.pc.CIA.value index = pc//4 diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 7262e1ce..39768bf1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -26,7 +26,7 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) - def test_sv_remap(self): + def test_sv_remap1(self): """>>> lst = ["svremap 2, 2, 3, 0", "sv.fmadds 0.v, 8.v, 16.v, 0.v" ] @@ -63,8 +63,9 @@ class DecoderTestCase(FHDLTestCase): res = [] # store FPs - for i, (x, y) in enumerate(zip(xf, yf)): + for i, x in enumerate(xf): fprs[i+16] = fp64toselectable(float(x)) # X matrix + for i, y in enumerate(yf): fprs[i+32] = fp64toselectable(float(y)) # Y matrix continue #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single @@ -96,6 +97,108 @@ class DecoderTestCase(FHDLTestCase): # self.assertEqual(sim.fpr(i+2), t) # self.assertEqual(sim.fpr(i+6), u) + def test_sv_remap2(self): + """>>> lst = ["svremap 5, 4, 3, 0", + "sv.fmadds 0.v, 8.v, 16.v, 0.v" + ] + REMAP fmadds FRT, FRA, FRC, FRB + """ + lst = SVP64Asm(["svremap 4, 3, 3, 0", + "sv.fmadds 0.v, 16.v, 32.v, 0.v" + ]) + lst = list(lst) + + # 3x2 matrix + X1 = [[1, 2, 3], + [3, 4, 5], + ] + # 2x3 matrix + Y1 = [[6, 7], + [8, 9], + [10, 11], + ] + + #### test matrices 2 + # 3x3 matrix + X2 = [[12,7,3], + [4 ,5,6], + [7 ,8,9], + ] + # 3x4 matrix + Y2 = [[5,8,1,2], + [6,7,3,0], + [4,5,9,1]] + + #### test matrices 3 + # 3x4 matrix + X3 = [[12,7,3], + [4 ,5,6], + [7 ,8,9], + [2 ,0,1]] + # 3x5 matrix + Y3 = [[5,8,1,2,3], + [6,7,3,0,9], + [4,5,9,1,2]] + + X = X2 + Y = Y2 + + # get the dimensions of the 2 matrices + xdim1 = len(X[0]) + ydim1 = len(X) + xdim2 = len(Y[0]) + ydim2 = len(Y) + + VL = ydim2 * xdim2 * ydim1 + print ("xdim2 ydim1 ydim2", xdim2, ydim1, ydim2) + + xf = reduce(operator.add, X) + yf = reduce(operator.add, Y) + print ("flattened X,Y") + print ("\t", xf) + print ("\t", yf) + + # and create a linear result2, same scheme + #result1 = [0] * (ydim1*xdim2) + + + res = [] + # store FPs + fprs = [0] * 64 + for i, x in enumerate(xf): + fprs[i+16] = fp64toselectable(float(x)) # X matrix + for i, y in enumerate(yf): + fprs[i+32] = fp64toselectable(float(y)) # Y matrix + continue + #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single + #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double + #res.append((t, u)) + #print ("FFT", i, "in", a, b, "coeff", c, "mul", + # mul, "res", t, u) + + # SVSTATE (in this case, VL=12, to cover all of matrix) + svstate = SVP64State() + svstate.vl[0:7] = VL # VL + svstate.maxvl[0:7] = VL # MAXVL + print ("SVSTATE", bin(svstate.spr.asint())) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_fprs=fprs) + print ("spr svshape0", sim.spr['SVSHAPE0']) + print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print ("spr svshape1", sim.spr['SVSHAPE1']) + print ("spr svshape2", sim.spr['SVSHAPE2']) + print ("spr svshape3", sim.spr['SVSHAPE3']) + for i in range(16): + print ("i", i, float(sim.fpr(i))) + # confirm that the results are as expected + #for i, (t, u) in enumerate(res): + # self.assertEqual(sim.fpr(i+2), t) + # self.assertEqual(sim.fpr(i+6), u) + def run_tst_program(self, prog, initial_regs=None, svstate=None, initial_mem=None,