From: Andreas Sandberg Date: Wed, 11 Feb 2015 15:23:27 +0000 (-0500) Subject: sim: Move the BaseTLB to src/arch/generic/ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=550c31849024a2184887df87aae39617ebfe0d6a;p=gem5.git sim: Move the BaseTLB to src/arch/generic/ The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh --- diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index ee59041f3..ccd4362d3 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -39,10 +39,10 @@ #include "arch/alpha/pagetable.hh" #include "arch/alpha/utility.hh" #include "arch/alpha/vtophys.hh" +#include "arch/generic/tlb.hh" #include "base/statistics.hh" #include "mem/request.hh" #include "params/AlphaTLB.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh index 6706b4724..870276b0a 100755 --- a/src/arch/arm/stage2_lookup.hh +++ b/src/arch/arm/stage2_lookup.hh @@ -47,7 +47,6 @@ #include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "mem/request.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f996f2d53..0be569fec 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -48,12 +48,12 @@ #include "arch/arm/pagetable.hh" #include "arch/arm/utility.hh" #include "arch/arm/vtophys.hh" +#include "arch/generic/tlb.hh" #include "base/statistics.hh" #include "dev/dma_device.hh" #include "mem/request.hh" #include "params/ArmTLB.hh" #include "sim/probe/pmu.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py new file mode 100644 index 000000000..6a8a9727f --- /dev/null +++ b/src/arch/generic/BaseTLB.py @@ -0,0 +1,34 @@ +# Copyright (c) 2008 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject + +class BaseTLB(SimObject): + type = 'BaseTLB' + abstract = True + cxx_header = "arch/generic/tlb.hh" diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index 9d59fa269..c87ad671f 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -33,4 +33,9 @@ if env['TARGET_ISA'] == 'null': Source('decode_cache.cc') Source('mmapped_ipr.cc') +Source('tlb.cc') + +SimObject('BaseTLB.py') + +DebugFlag('TLB') Source('pseudo_inst.cc') diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc new file mode 100644 index 000000000..39ea09b0d --- /dev/null +++ b/src/arch/generic/tlb.cc @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/generic/tlb.hh" + +#include "cpu/thread_context.hh" +#include "mem/page_table.hh" +#include "sim/faults.hh" +#include "sim/full_system.hh" +#include "sim/process.hh" + +Fault +GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode) +{ + if (FullSystem) + panic("Generic translation shouldn't be used in full system mode.\n"); + + Process * p = tc->getProcessPtr(); + + Fault fault = p->pTable->translate(req); + if(fault != NoFault) + return fault; + + return NoFault; +} + +void +GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode) +{ + assert(translation); + translation->finish(translateAtomic(req, tc, mode), req, tc, mode); +} + +Fault +GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +{ + return NoFault; +} + +void +GenericTLB::demapPage(Addr vaddr, uint64_t asn) +{ + warn("Demapping pages in the generic TLB is unnecessary.\n"); +} diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh new file mode 100644 index 000000000..0a7e78151 --- /dev/null +++ b/src/arch/generic/tlb.hh @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_GENERIC_TLB_HH__ +#define __ARCH_GENERIC_TLB_HH__ + +#include "base/misc.hh" +#include "mem/request.hh" +#include "sim/sim_object.hh" + +class ThreadContext; +class BaseMasterPort; + +class BaseTLB : public SimObject +{ + protected: + BaseTLB(const Params *p) + : SimObject(p) + {} + + public: + enum Mode { Read, Write, Execute }; + + public: + virtual void demapPage(Addr vaddr, uint64_t asn) = 0; + + /** + * Remove all entries from the TLB + */ + virtual void flushAll() = 0; + + /** + * Take over from an old tlb context + */ + virtual void takeOverFrom(BaseTLB *otlb) = 0; + + /** + * Get the table walker master port if present. This is used for + * migrating port connections during a CPU takeOverFrom() + * call. For architectures that do not have a table walker, NULL + * is returned, hence the use of a pointer rather than a + * reference. + * + * @return A pointer to the walker master port or NULL if not present + */ + virtual BaseMasterPort* getMasterPort() { return NULL; } + + void memInvalidate() { flushAll(); } + + class Translation + { + public: + virtual ~Translation() + {} + + /** + * Signal that the translation has been delayed due to a hw page table + * walk. + */ + virtual void markDelayed() = 0; + + /* + * The memory for this object may be dynamically allocated, and it may + * be responsible for cleaning itself up which will happen in this + * function. Once it's called, the object is no longer valid. + */ + virtual void finish(const Fault &fault, RequestPtr req, + ThreadContext *tc, Mode mode) = 0; + + /** This function is used by the page table walker to determine if it + * should translate the a pending request or if the underlying request + * has been squashed. + * @ return Is the instruction that requested this translation squashed? + */ + virtual bool squashed() const { return false; } + }; +}; + +class GenericTLB : public BaseTLB +{ + protected: + GenericTLB(const Params *p) + : BaseTLB(p) + {} + + public: + void demapPage(Addr vaddr, uint64_t asn); + + Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode); + + + /** + * Do post-translation physical address finalization. + * + * This method is used by some architectures that need + * post-translation massaging of physical addresses. For example, + * X86 uses this to remap physical addresses in the APIC range to + * a range of physical memory not normally available to real x86 + * implementations. + * + * @param req Request to updated in-place. + * @param tc Thread context that created the request. + * @param mode Request type (read/write/execute). + * @return A fault on failure, NoFault otherwise. + */ + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; +}; + +#endif // __ARCH_GENERIC_TLB_HH__ diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 225e207dc..c7cd5e631 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -37,6 +37,7 @@ #include +#include "arch/generic/tlb.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/pagetable.hh" #include "arch/mips/utility.hh" @@ -45,7 +46,6 @@ #include "mem/request.hh" #include "params/MipsTLB.hh" #include "sim/sim_object.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 0abafc777..9818774d8 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -39,6 +39,7 @@ #include +#include "arch/generic/tlb.hh" #include "arch/power/isa_traits.hh" #include "arch/power/pagetable.hh" #include "arch/power/utility.hh" @@ -46,7 +47,6 @@ #include "base/statistics.hh" #include "mem/request.hh" #include "params/PowerTLB.hh" -#include "sim/tlb.hh" class ThreadContext; diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 9c027cbbd..1d229fba7 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,12 +31,12 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "arch/generic/tlb.hh" #include "arch/sparc/asi.hh" #include "arch/sparc/tlb_map.hh" #include "base/misc.hh" #include "mem/request.hh" #include "params/SparcTLB.hh" -#include "sim/tlb.hh" class ThreadContext; class Packet; diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index b43cda36a..b9eb85e21 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -42,10 +42,10 @@ #include +#include "arch/generic/tlb.hh" #include "base/bitunion.hh" #include "base/misc.hh" #include "sim/faults.hh" -#include "sim/tlb.hh" namespace X86ISA { diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index e1089f90c..77f9fc49d 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -44,6 +44,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/x86/regs/segment.hh" #include "arch/x86/pagetable.hh" #include "base/trie.hh" @@ -51,7 +52,6 @@ #include "mem/request.hh" #include "params/X86TLB.hh" #include "sim/sim_object.hh" -#include "sim/tlb.hh" class ThreadContext; class Packet; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 108b799e1..ab275369f 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -51,6 +51,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/utility.hh" #include "base/trace.hh" #include "config/the_isa.hh" @@ -65,7 +66,6 @@ #include "mem/packet.hh" #include "sim/byteswap.hh" #include "sim/system.hh" -#include "sim/tlb.hh" /** * @file diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index d6a8bd032..229066fcc 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -44,6 +44,7 @@ #include #include +#include "arch/generic/tlb.hh" #include "arch/kernel_stats.hh" #include "arch/vtophys.hh" #include "cpu/checker/cpu.hh" @@ -53,7 +54,6 @@ #include "cpu/thread_context.hh" #include "params/CheckerCPU.hh" #include "sim/full_system.hh" -#include "sim/tlb.hh" using namespace std; using namespace TheISA; diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh index f870a9c11..4ff75546a 100644 --- a/src/cpu/translation.hh +++ b/src/cpu/translation.hh @@ -45,8 +45,8 @@ #ifndef __CPU_TRANSLATION_HH__ #define __CPU_TRANSLATION_HH__ +#include "arch/generic/tlb.hh" #include "sim/faults.hh" -#include "sim/tlb.hh" /** * This class captures the state of an address translation. A translation diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py deleted file mode 100644 index 8a03413a9..000000000 --- a/src/sim/BaseTLB.py +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2008 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -from m5.SimObject import SimObject - -class BaseTLB(SimObject): - type = 'BaseTLB' - abstract = True - cxx_header = "sim/tlb.hh" diff --git a/src/sim/SConscript b/src/sim/SConscript index 7583b53cb..400d595e3 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,7 +30,6 @@ Import('*') -SimObject('BaseTLB.py') SimObject('ClockedObject.py') SimObject('TickedObject.py') SimObject('Root.py') @@ -75,7 +74,6 @@ if env['TARGET_ISA'] != 'null': Source('process.cc') Source('pseudo_inst.cc') Source('syscall_emul.cc') - Source('tlb.cc') DebugFlag('Checkpoint') DebugFlag('Config') @@ -92,7 +90,6 @@ DebugFlag('PseudoInst') DebugFlag('Stack') DebugFlag('SyscallVerbose') DebugFlag('TimeSync') -DebugFlag('TLB') DebugFlag('Thread') DebugFlag('Timer') DebugFlag('VtoPhys') diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc deleted file mode 100644 index 00a51dbe3..000000000 --- a/src/sim/tlb.cc +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "cpu/thread_context.hh" -#include "mem/page_table.hh" -#include "sim/faults.hh" -#include "sim/full_system.hh" -#include "sim/process.hh" -#include "sim/tlb.hh" - -Fault -GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode) -{ - if (FullSystem) - panic("Generic translation shouldn't be used in full system mode.\n"); - - Process * p = tc->getProcessPtr(); - - Fault fault = p->pTable->translate(req); - if(fault != NoFault) - return fault; - - return NoFault; -} - -void -GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, Mode mode) -{ - assert(translation); - translation->finish(translateAtomic(req, tc, mode), req, tc, mode); -} - -Fault -GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const -{ - return NoFault; -} - -void -GenericTLB::demapPage(Addr vaddr, uint64_t asn) -{ - warn("Demapping pages in the generic TLB is unnecessary.\n"); -} diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh deleted file mode 100644 index 9557fa3b1..000000000 --- a/src/sim/tlb.hh +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2011 ARM Limited - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __SIM_TLB_HH__ -#define __SIM_TLB_HH__ - -#include "base/misc.hh" -#include "mem/request.hh" -#include "sim/sim_object.hh" - -class ThreadContext; -class BaseMasterPort; - -class BaseTLB : public SimObject -{ - protected: - BaseTLB(const Params *p) - : SimObject(p) - {} - - public: - enum Mode { Read, Write, Execute }; - - public: - virtual void demapPage(Addr vaddr, uint64_t asn) = 0; - - /** - * Remove all entries from the TLB - */ - virtual void flushAll() = 0; - - /** - * Take over from an old tlb context - */ - virtual void takeOverFrom(BaseTLB *otlb) = 0; - - /** - * Get the table walker master port if present. This is used for - * migrating port connections during a CPU takeOverFrom() - * call. For architectures that do not have a table walker, NULL - * is returned, hence the use of a pointer rather than a - * reference. - * - * @return A pointer to the walker master port or NULL if not present - */ - virtual BaseMasterPort* getMasterPort() { return NULL; } - - void memInvalidate() { flushAll(); } - - class Translation - { - public: - virtual ~Translation() - {} - - /** - * Signal that the translation has been delayed due to a hw page table - * walk. - */ - virtual void markDelayed() = 0; - - /* - * The memory for this object may be dynamically allocated, and it may - * be responsible for cleaning itself up which will happen in this - * function. Once it's called, the object is no longer valid. - */ - virtual void finish(const Fault &fault, RequestPtr req, - ThreadContext *tc, Mode mode) = 0; - - /** This function is used by the page table walker to determine if it - * should translate the a pending request or if the underlying request - * has been squashed. - * @ return Is the instruction that requested this translation squashed? - */ - virtual bool squashed() const { return false; } - }; -}; - -class GenericTLB : public BaseTLB -{ - protected: - GenericTLB(const Params *p) - : BaseTLB(p) - {} - - public: - void demapPage(Addr vaddr, uint64_t asn); - - Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); - void translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, Mode mode); - - - /** - * Do post-translation physical address finalization. - * - * This method is used by some architectures that need - * post-translation massaging of physical addresses. For example, - * X86 uses this to remap physical addresses in the APIC range to - * a range of physical memory not normally available to real x86 - * implementations. - * - * @param req Request to updated in-place. - * @param tc Thread context that created the request. - * @param mode Request type (read/write/execute). - * @return A fault on failure, NoFault otherwise. - */ - Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; -}; - -#endif // __ARCH_SPARC_TLB_HH__