From: Simon Marchi Date: Wed, 10 Feb 2016 15:10:18 +0000 (-0500) Subject: arm-tdep.c: Fix typo X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=550dc4e26630c9b9a2bb95cd51250762fc89fe16;p=binutils-gdb.git arm-tdep.c: Fix typo unpriveleged -> unprivileged gdb/ChangeLog: * arm-tdep.c (arm_copy_extra_ld_st): Fix "unpriveleged" typo. (arm_decode_dp_misc): Likewise. --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 05d6cd07529..07411d87846 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2016-02-10 Simon Marchi + + * arm-tdep.c (arm_copy_extra_ld_st): Fix "unpriveleged" typo. + (arm_decode_dp_misc): Likewise. + 2016-02-10 Marcin Kościelnicki * amd64-tdep.c (amd64_ax_pseudo_register_collect): New function. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 5a2d490df77..6ac05f076b8 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -5420,7 +5420,7 @@ cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, transfers, which have a different encoding to byte/word transfers. */ static int -arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, +arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int op1 = bits (insn, 20, 24); @@ -5439,7 +5439,7 @@ arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " - "insn %.8lx\n", unpriveleged ? "unpriveleged " : "", + "insn %.8lx\n", unprivileged ? "unprivileged " : "", (unsigned long) insn); opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; @@ -6549,7 +6549,7 @@ arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, else if ((op1 & 0x10) == 0x10 && op2 == 0x9) return arm_copy_unmodified (gdbarch, insn, "synch", dsc); else if (op2 == 0xb || (op2 & 0xd) == 0xd) - /* 2nd arg means "unpriveleged". */ + /* 2nd arg means "unprivileged". */ return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, dsc); }