From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Oct 2022 23:26:23 +0000 (+0100)
Subject: no svstate instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=551b5acbae7d905b2db30c64454d5c831f868f88;p=openpower-isa.git

no svstate instruction
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c1610c4e..3b94fe2c 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1692,8 +1692,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         self.reset_remaps()
-        if (self.is_svp64_mode or ins_name in ['svstep',
-          'svremap', 'svstate']):
+        if (self.is_svp64_mode or ins_name in ['svstep', 'svremap']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode:
             pre = yield from self.update_new_svstate_steps()