From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Jul 2020 16:22:35 +0000 (+0100)
Subject: allow qemu to stop at specified end point
X-Git-Tag: div_pipeline~154
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5524b1aefead008063fc168a28734ee3b38db92c;p=soc.git

allow qemu to stop at specified end point
---

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 39a1fd90..dac8c170 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -11,7 +11,8 @@ from soc.regfile.regfiles import FastRegs
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
                        msr=0,
-                       do_sim=True):
+                       do_sim=True,
+                       extra_break_addr=None):
 
         self.program = program
         self.name = name
@@ -28,6 +29,7 @@ class TestCase:
         self.mem = mem
         self.msr = msr
         self.do_sim = do_sim
+        self.extra_break_addr = extra_break_addr
 
 
 class ALUHelpers:
diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py
index 97d1e998..8801844d 100644
--- a/src/soc/simulator/test_helloworld_sim.py
+++ b/src/soc/simulator/test_helloworld_sim.py
@@ -38,13 +38,14 @@ class HelloTestCases(FHDLTestCase):
                 "mtspr   9, 12",     # mtctr r12
                 "bcctrl  20,0,0", # bctrl
                 ]
-        self.run_tst_program(Program(lst), [1,12])
+        self.run_tst_program(Program(lst), [1,12], extra_break_addr=0x1014)
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
-                                    initial_mem=None):
+                                    initial_mem=None, extra_break_addr=None):
         initial_regs = [0] * 32
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
-                                            initial_mem, 0)
+                                            initial_mem, 0,
+                                            extra_break_addr=extra_break_addr)
         self.test_data.append(tc)
 
 
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 51d4e7a1..387803c3 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -276,12 +276,13 @@ class DecoderBase:
 
         return simulator
 
-    def run_tst_program(self, prog, reglist, initial_mem=None):
+    def run_tst_program(self, prog, reglist, initial_mem=None,
+                                             extra_break_addr=None):
         import sys
         simulator = self.run_tst(prog, initial_mem=initial_mem,
                                  initial_pc=0x20000000)
         prog.reset()
-        with run_program(prog, initial_mem) as q:
+        with run_program(prog, initial_mem, extra_break_addr) as q:
             self.qemu_register_compare(simulator, q, reglist)
             self.qemu_mem_compare(simulator, q, True)
         print(simulator.gpr.dump())