From: Francisco Jerez Date: Thu, 8 Nov 2018 22:03:24 +0000 (-0800) Subject: intel/fs: Prevent emission of IR instructions not aligned to their own execution... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=552642066f511960c7fa7c0fdf1bf733982fc1c9;p=mesa.git intel/fs: Prevent emission of IR instructions not aligned to their own execution size. This can occur during payload setup of SIMD-split send message instructions, which can lead to the emission of header setup instructions with a non-zero channel group and fixed SIMD width. Such instructions could end up using undefined channel enable signals except they don't care since they're always marked force_writemask_all. Not known to affect correctness of any workload at this point, but it would be trivial to back-port to stable if something comes up. Reported-by: Sagar Ghuge Reviewed-by: Matt Turner Tested-by: Sagar Ghuge --- diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 0cafaf50e56..4846820722c 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -114,11 +114,25 @@ namespace brw { fs_builder group(unsigned n, unsigned i) const { - assert(force_writemask_all || - (n <= dispatch_width() && i < dispatch_width() / n)); fs_builder bld = *this; + + if (n <= dispatch_width() && i < dispatch_width() / n) { + bld._group += i * n; + } else { + /* The requested channel group isn't a subset of the channel group + * of this builder, which means that the resulting instructions + * would use (potentially undefined) channel enable signals not + * specified by the parent builder. That's only valid if the + * instruction doesn't have per-channel semantics, in which case + * we should clear off the default group index in order to prevent + * emitting instructions with channel group not aligned to their + * own execution size. + */ + assert(force_writemask_all); + bld._group = 0; + } + bld._dispatch_width = n; - bld._group += i * n; return bld; }