From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Apr 2020 14:47:10 +0000 (+0100)
Subject: mention trap on illegal instruction
X-Git-Tag: convert-csv-opcode-to-binary~2840
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5528d704c90ef121ecae191ca6c10ecbd7193bdd;p=libreriscv.git

mention trap on illegal instruction
---

diff --git a/openpower/isans_letter.mdwn b/openpower/isans_letter.mdwn
index f07fbfc03..943f8be51 100644
--- a/openpower/isans_letter.mdwn
+++ b/openpower/isans_letter.mdwn
@@ -33,7 +33,7 @@ with people who can help us.
   Broadcom VideoCore IV being based around extensions to an ARC core).
 * Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux
   distributions will very deliberately run unmodified on our ISA,
-  including full compatibility with illegal instruction requirements.
+  including full compatibility with illegal instruction trap requirements.
 
 ## One CPU multiple ISAs