From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 27 Mar 2019 20:15:14 +0000 (+0100)
Subject: soc/interconnect/axi: remove dead code (thanks gsomlo)
X-Git-Tag: 24jan2021_ls180~1357
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=552b0243b398502d6140715139c1739227851b0f;p=litex.git

soc/interconnect/axi: remove dead code (thanks gsomlo)
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 7d0792ce..a110c36d 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -78,8 +78,6 @@ class AXI2Wishbone(Module):
                 NextState("DO-WRITE")
             )
         )
-        axi_ar_addr = Signal(32)
-        self.comb += axi_ar_addr.eq(axi.ar.addr - base_address)
         fsm.act("DO-READ",
             wishbone.stb.eq(1),
             wishbone.cyc.eq(1),