From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 May 2015 10:28:49 +0000 (+0200)
Subject: soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
X-Git-Tag: 24jan2021_ls180~2262
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=553262bcc14cf112f50eb473cb592f7d0f6958f8;p=litex.git

soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
---

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 1d96d280..44ad29bc 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -59,8 +59,8 @@ class SDRAMSoC(SoC):
 
             l2_size = self.sdram_controller_settings.l2_size
             if l2_size:
-                # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
-                # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
+                # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
+                # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
                 # Remove this workaround when fixed by Xilinx.
                 from mibuild.xilinx.vivado import XilinxVivadoToolchain
                 if isinstance(self.platform.toolchain, XilinxVivadoToolchain):