From: lkcl <lkcl@web>
Date: Sat, 10 Sep 2022 12:25:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~522
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5534c4923d4919721d4d236af464a3ddf2e261bf;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 00e8fdc9a..809b4d324 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -45,10 +45,13 @@ Allocation of not just Simple-V but the 80-100 Scalar instructions all
 at the same time*.
 
 It is also critical to note that Simple-V **does not modify the Scalar
-Power ISA in any way**. The sole semi-exception to that is Vectorised
+Power ISA in any way** and neither must Vectorised instructions be
+different from their Scalar words.
+The sole exception to that is Vectorised
 Branch Conditional, in order to provide the usual Advanced Branching
-capability present in every Commercial 3D GPU ISA. Scalar Branch is
-**not** modified by the **Vectorised** variant.
+capability present in every Commercial 3D GPU ISA, but it
+is the *Vectorised* Branch-Conditional that is augmented, not Scalar
+Branch.
 
 # Compliancy Levels