From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Sep 2022 21:00:15 +0000 (+0100)
Subject: add bc_ctr and bc_cti but not used yet
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55364ba2f84a15c9292327d48ee850b797be35ca;p=openpower-isa.git

add bc_ctr and bc_cti but not used yet
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 40fdc0ef..5fab53d1 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1146,11 +1146,11 @@ class SVP64Asm:
             elif is_bc:
                 if encmode == 'all':
                     bc_all = 1
-                elif encmode == 'st':  # svstep mode
-                    bc_step = 1
-                elif encmode == 'sr':  # svstep BRc mode
-                    bc_step = 1
-                    bc_brc = 1
+                elif encmode == 'ctr':  # ctr-test mode
+                    bc_ctr = 1
+                elif encmode == 'cti':  # ctr-test with inclusive mode
+                    bc_ctr = 1
+                    bc_cti = 1
                 elif encmode == 'vs':  # VLSET mode
                     bc_vlset = 1
                 elif encmode == 'vsi':  # VLSET mode with VLI (VL inclusives)