From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 24 Jul 2020 13:42:04 +0000 (+0100)
Subject: too much debug info going past, so add the test registers to the
X-Git-Tag: semi_working_ecp5~568
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5538d058b6ae6c0124036d56ecb94a32907f42be;p=soc.git

too much debug info going past, so add the test registers to the
failed log message
---

diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py
index e822e41c..5404c773 100644
--- a/src/soc/fu/div/test/runner.py
+++ b/src/soc/fu/div/test/runner.py
@@ -190,6 +190,7 @@ class DivRunner(unittest.TestCase):
                         # XXX print("time:", sim._state.timeline.now)
                         msg = "%s: %s" % (self.div_pipe_kind.name, code)
                         msg += " %s" % (repr(prog.assembly))
+                        msg += " %s" % (repr(test.regs))
                         yield from self.check_alu_outputs(alu, pdecode2,
                                                           isa_sim, msg)