From: lkcl <lkcl@web>
Date: Wed, 14 Jul 2021 12:53:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~621
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55470ebf2b0b14cb365d0f4acc29c0d603302f07;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 397a9e609..3b6560aaa 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -78,6 +78,10 @@ The format of the SVSTATE SPR is as follows:
 | 21:27 | dststep  | for dststep = 0..VL-1 |
 | 28:29 | subvl    | Sub-vector length     |
 | 30:31 | svstep   | for svstep = 0..SUBVL-1  |
+| 32:36 | SVRen    | REMAP enable          |
+| 37:61 | rsvd     | reserved              |
+| 62    | RMpst    | REMAP persistence     |
+| 63    | vfirst   | Vertical First mode   |
 
 The relationship between SUBVL and the subvl field is: