From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 May 2020 00:11:49 +0000 (+0100)
Subject: mention zeroing
X-Git-Tag: div_pipeline~855
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=555bab5c6431951aab359cc31ba31ede9c12f64f;p=soc.git

mention zeroing
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 4749f4a3..048e5b4c 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -259,6 +259,8 @@ class LDSTCompUnit(Elaboratable):
         alu_o = Signal(self.rwid, reset_less=True)
         ldd_o = Signal(self.rwid, reset_less=True)
 
+        # XXX TODO ZEROing just lije in ComUnit
+
         # select immediate or src2 reg to add
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)