From: rwilbur <rwilbur@web>
Date: Tue, 16 Mar 2021 22:48:24 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5571d2c456fdd5ba124bbf3d8f17c951ae6b558d;p=libreriscv.git

---

diff --git a/rwilbur.mdwn b/rwilbur.mdwn
index 19fa56ed0..639e01546 100644
--- a/rwilbur.mdwn
+++ b/rwilbur.mdwn
@@ -16,6 +16,6 @@ Working on the [[multiplication|/3d_gpu/architecture/dynamic_simd/mul]] wiki pag
 
 Working on [Bug 602 - low performance bare minimum functionality SIMD emulator required][bug 602] pulling pseudocode out of documentation to make a VSX implementation in software.  Based on the ISA spec. v3.0B:
 
-1.  pp. 246 to 252, vector pack/unpack
+1.  pp. 246 to 252, vector pack/unpack (Looks like section 6.8 "Vector Permute and Formatting Instructions", subsection 6.8.1 "Vector Pack and Unpack Instructions" actually appears on pages labeled 248-254 which are actually pages 266-272)
 
 [bug 602]:  https://bugs.libre-soc.org/show_bug.cgi?id=602