From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 16:40:41 +0000 (+0000) Subject: increment CRs based on srcstep, see what happens X-Git-Tag: convert-csv-opcode-to-binary~199 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=557351e7da53e4f09b16fe9b729ddd425ff04a15;p=soc.git increment CRs based on srcstep, see what happens --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index a5fde3b3..8a3591fe 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -1168,7 +1168,10 @@ class PowerDecode2(PowerDecodeSubset): comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA) - comb += to_reg.data.eq(svdec.cr_out) # 7-bit output + with m.If(svdec.isvec): + comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output + with m.Else(): + comb += to_reg.data.eq(svdec.cr_out) # 7-bit output comb += to_reg.ok.eq(fromreg.ok) # sigh this is exactly the sort of thing for which the