From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Dec 2021 17:47:36 +0000 (+0000)
Subject: raise a MemException in ISACaller RADIXMMU
X-Git-Tag: sv_maxu_works-initial~666
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=559715c30fbea5f3ce0a48f35046cc03a4b053a7;p=openpower-isa.git

raise a MemException in ISACaller RADIXMMU
and capture it in ISACaller, and throw TRAP 0x300
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 51dfd6fe..604bc204 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1018,13 +1018,19 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         try:
             yield from self.call(opname)         # execute the instruction
         except MemException as e:                # check for memory errors
-            if e.args[0] != 'unaligned':         # only doing aligned at the mo
-                raise e                          # ... re-raise
-            # run a Trap but set DAR first
-            print ("memory unaligned exception, DAR", e.dar)
-            self.spr['DAR'] = SelectableInt(e.dar, 64)
-            self.call_trap(0x600, PIb.PRIV)                # 0x600, privileged
-            return
+            if e.args[0] == 'unaligned':         # alignment error
+               # run a Trap but set DAR first
+                print ("memory unaligned exception, DAR", e.dar)
+                self.spr['DAR'] = SelectableInt(e.dar, 64)
+                self.call_trap(0x600, PIb.PRIV)    # 0x600, privileged
+                return
+            elif e.args[0] == 'invalid':         # invalid
+               # run a Trap but set DAR first
+                log ("RADIX MMU memory invalid error")
+                self.call_trap(0x300, PIb.PRIV)    # 0x300, privileged
+                return
+            # not supported yet:
+            raise e                          # ... re-raise
 
         # don't use this except in special circumstances
         if not self.respect_pc:
diff --git a/src/openpower/decoder/isa/radixmmu.py b/src/openpower/decoder/isa/radixmmu.py
index c647777f..9fe724d9 100644
--- a/src/openpower/decoder/isa/radixmmu.py
+++ b/src/openpower/decoder/isa/radixmmu.py
@@ -18,7 +18,7 @@ from copy import copy
 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from openpower.decoder.helpers import exts, gtu, ltu, undefined
-from openpower.decoder.isa.mem import Mem
+from openpower.decoder.isa.mem import Mem, MemException
 from openpower.consts import MSRb  # big-endian (PowerISA versions)
 
 import math
@@ -444,7 +444,7 @@ class RADIX:
 
         # WIP
         if mbits == 0:
-            return "invalid"
+            raise MemException("invalid")
 
         # mask_size := mbits(4 downto 0);
         mask_size = mbits[0:5]
@@ -487,7 +487,7 @@ class RADIX:
 
             print("    valid, leaf", valid, leaf)
             if not valid:
-                return "invalid" # TODO: return error
+                raise MemException("invalid")
             if leaf:
                 print ("is leaf, checking perms")
                 ok = self._check_perms(data, priv, mode)