From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Jun 2021 12:26:19 +0000 (+0100)
Subject: add an explicit PowerDecoder.is_svp64_mode flag to help with detection
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55a5f9837e41f322170a4c2bb52ebf2141d3fe93;p=soc.git

add an explicit PowerDecoder.is_svp64_mode flag to help with detection
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 842b5eac..a95750cc 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -111,6 +111,7 @@ class NonProductionCore(Elaboratable):
         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
         if self.svp64_en:
             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
+            self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
             self.sv_pred_sm = Signal() # TODO: SIMD width
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
@@ -131,6 +132,7 @@ class NonProductionCore(Elaboratable):
             fnunit = fu.fnunit.value
             opkls = fu.opsubsetkls
             if f_name == 'TRAP':
+                # TRAP decoder is the *main* decoder
                 self.trapunit = funame
                 continue
             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
@@ -170,6 +172,7 @@ class NonProductionCore(Elaboratable):
                 comb += v.pred_dm.eq(self.sv_pred_dm)
                 if k != self.trapunit:
                     comb += v.sv_rm.eq(self.sv_rm) # pass through SVP64 ReMap
+                    comb += v.is_svp64_mode.eq(self.is_svp64_mode)
 
         # ssh, cheat: trap uses the main decoder because of the rewriting
         self.des[self.trapunit] = self.e.do
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 8bf44ae6..879a455a 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -337,6 +337,7 @@ class TestIssuerInternal(Elaboratable):
                         comb += svp64.bigendian.eq(self.core_bigendian_i)
                         # pass the decoded prefix (if any) to PowerDecoder2
                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
+                        sync += pdecode2.is_svp64_mode.eq(is_svp64_mode)
                         # remember whether this is a prefixed instruction, so
                         # the FSM can readily loop when VL==0
                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
@@ -745,6 +746,8 @@ class TestIssuerInternal(Elaboratable):
                     sync += core.sv_rm.eq(pdecode2.sv_rm)
                     # set RA_OR_ZERO detection in satellite decoders
                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+                    # and svp64 detection
+                    sync += core.is_svp64_mode.eq(is_svp64_mode)
 
                 m.next = "INSN_EXECUTE"  # move to "execute"