From: Shriya Sharma Date: Wed, 18 Oct 2023 11:44:02 +0000 (+0100) Subject: mention limitations of not having dsrd clearly X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55a743f433452656276a9502d1299e6440ebf6e8;p=libreriscv.git mention limitations of not having dsrd clearly --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index d535a9396..26365a836 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -316,6 +316,13 @@ and this is precisely what `adde` already does. For multiply, divide and shift it is worthwhile to use one scalar register effectively as a full 64-bit carry/chain. +The limitations of this approach therefore become pretty clear: +not only must Vertical-First Mode be used but also the predication +with zeroing trick. Worse than that, an entire temporary vector +is required which wastes register space. +A better way would be to create a single +scalar instruction that can do the long-shift in-place. + The basic principle of the 3-in 2-out `dsrd` is: ```