From: lkcl Date: Sun, 10 Apr 2022 23:53:10 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2797 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55a7b72a540e7d6b305aff8dab738e62eb90e750;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index feba1ab45..8155473b7 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -201,14 +201,13 @@ on context after decoding of the Scalar suffix: | EXTRA | `10:18` | Register Extra encoding | | MODE | `19:23` | changes Vector behaviour | - * MODE changes the behaviour of the SV operation (result saturation, mapreduce) * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR). * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix. -Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag. +Similar to OpenPOWER `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag. Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.