From: lkcl Date: Mon, 5 Sep 2022 14:43:24 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~681 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55b6d44e870f6585a73e703a9a8356d28c13c054;p=libreriscv.git --- diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 86ae3b4de..ca1eb1539 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -39,7 +39,7 @@ When Rc=1 the CR element however is still stored in the CR regfile, even if the basic structure packing on sub-elements. Bits 4-5 (normally elwidth) are taken up as Pack/Unpack bits. Saturation may be simultaneously enabled. -Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL. +Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. simple, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL. The Mode table for Arithmetic and Logical operations is laid out as follows: