From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Nov 2019 11:56:31 +0000 (+0100)
Subject: Correctly treat empty modules as blackboxes in Verific
X-Git-Tag: working-ls180~955^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55bda2b2c693a7ff79da545e7b52901de00df475;p=yosys.git

Correctly treat empty modules as blackboxes in Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c2086afa4..de41e1a5c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -130,7 +130,7 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net)
 
 bool is_blackbox(Netlist *nl)
 {
-	if (nl->IsBlackBox())
+	if (nl->IsBlackBox() || nl->IsEmptyBox())
 		return true;
 
 	const char *attr = nl->GetAttValue("blackbox");