From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Aug 2019 14:26:54 +0000 (+0200)
Subject: Fix port hanlding in pmgen
X-Git-Tag: working-ls180~1102^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55bf8f69e085caa0a3f0ccae8bf231f77aba6bbc;p=yosys.git

Fix port hanlding in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index c2621393d..573722d68 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -422,8 +422,6 @@ with open(outfile, "w") as f:
     print("  void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
     print("    for (auto bit : sigmap(sig)) {", file=f)
     print("      if (bit.wire == nullptr) continue;", file=f)
-    print("      if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f)
-    print("        sigusers[bit].insert(nullptr);", file=f)
     print("      sigusers[bit].insert(cell);", file=f)
     print("    }", file=f)
     print("  }", file=f)
@@ -478,10 +476,11 @@ with open(outfile, "w") as f:
             else:
                 print("    ud_{}.{} = {}();".format(current_pattern, s, t), file=f)
     current_pattern = None
-    print("    for (auto cell : module->cells()) {", file=f)
+    print("    for (auto port : module->ports)", file=f)
+    print("      add_siguser(module->wire(port), nullptr);", file=f)
+    print("    for (auto cell : module->cells())", file=f)
     print("      for (auto &conn : cell->connections())", file=f)
     print("        add_siguser(conn.second, cell);", file=f)
-    print("    }", file=f)
     print("    for (auto cell : cells) {", file=f)
 
     for index in range(len(blocks)):