From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 13 Jul 2020 09:58:47 +0000 (+0200)
Subject: Fix gearing
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55c66dc92a4fec49bb232388806df4b237f710ae;p=gram.git

Fix gearing
---

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 0841ea2..dda05f2 100644
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -58,7 +58,7 @@ class DDR3SoC(SoC, Elaboratable):
             write_latency=cwl_sys_latency
         )
 
-        ddrmodule = MT41K256M16(clk_freq, "1:4")
+        ddrmodule = MT41K256M16(clk_freq, "1:2")
         self.ddrphy = FakePHY(module=ddrmodule,
             settings=physettings,
             verbosity=SDRAM_VERBOSE_DBG)