From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 11:46:39 +0000 (+0100)
Subject: test trap, shift and condition
X-Git-Tag: div_pipeline~1496
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55ca51ca20528e0c794c32bb1c28e719a703f7e3;p=soc.git

test trap, shift and condition
---

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 113b37eb..0dc41784 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -72,8 +72,10 @@ class PyISAWriter(ISA):
 
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('fixedtrap')
+    isa.write_pysource('fixedshift')
     exit(0)
+    isa.write_pysource('condition')
+    isa.write_pysource('fixedtrap')
     isa.write_pysource('branch')
     isa.write_pysource('fixedlogical')
     isa.write_pysource('fixedstore')