From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 15:28:24 +0000 (+0100)
Subject: add overflow div tests
X-Git-Tag: div_pipeline~102
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55d936323a06c87737dcb21238dc540bb9368f5d;p=soc.git

add overflow div tests
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index dd7d0153..904cf30b 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -140,6 +140,27 @@ class DIVTestCase(FHDLTestCase):
         initial_regs[2] = 0xffc868bf4573da0b
         self.run_tst_program(Program(lst), initial_regs)
 
+    def test_divw_by_zero_1(self):
+        lst = ["divw. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1
+        initial_regs[2] = 0x0
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_divw_overflow2(self):
+        lst = ["divw. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x80000000
+        initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_divw_overflow3(self):
+        lst = ["divw. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x80000000
+        initial_regs[2] = 0xffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_rand_divw(self):
         insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):