From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 29 Jun 2020 12:46:59 +0000 (+0200)
Subject: Define PLL's PHASELOADREG input
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55dece5bcf3d0c59f40d10c4dc8ae92786a52c31;p=gram.git

Define PLL's PHASELOADREG input
---

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 769e2da..90f874a 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -68,6 +68,7 @@ class PLL(Elaboratable):
                        i_PHASESEL1=1,
                        i_PHASEDIR=0,
                        i_PHASESTEP=0,
+                       i_PHASELOADREG=0,
                        i_PLLWAKESYNC=0,
                        i_ENCLKOP=1,
                        i_ENCLKOS=1,