From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 26 Jun 2015 23:20:21 +0000 (-0700)
Subject: i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55dfd39b5f18f820694cad74ce40a3e0d3d6a0c4;p=mesa.git

i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.

This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs,
which controls whether or not to use SIMD8 geometry shaders.

For now, we control it via a new environment variable, INTEL_SCALAR_GS.
This provides a convenient way to try it out.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
index 6a9799e578e..742bac4e8ef 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -90,6 +90,7 @@ struct brw_compiler {
    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
 
    bool scalar_vs;
+   bool scalar_gs;
    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
 };
 
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index dc59b06bac1..ed0890f430f 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -57,6 +57,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
                     struct brw_geometry_program *gp,
                     struct brw_gs_prog_key *key)
 {
+   struct brw_compiler *compiler = brw->intelScreen->compiler;
    struct gl_shader *shader = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
    struct brw_stage_state *stage_state = &brw->gs.base;
    struct brw_gs_prog_data prog_data;
@@ -86,7 +87,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
    prog_data.base.base.nr_image_params = gs->NumImages;
 
    brw_nir_setup_glsl_uniforms(gp->program.Base.nir, prog, &gp->program.Base,
-                               &prog_data.base.base, false);
+                               &prog_data.base.base, compiler->scalar_gs);
 
    GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
 
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d910e479c9d..0ac4f2f6e0d 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -79,6 +79,8 @@ is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
    case MESA_SHADER_FRAGMENT:
    case MESA_SHADER_COMPUTE:
       return true;
+   case MESA_SHADER_GEOMETRY:
+      return compiler->scalar_gs;
    case MESA_SHADER_VERTEX:
       return compiler->scalar_vs;
    default:
@@ -101,6 +103,9 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
       compiler->scalar_vs = true;
 
+   if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
+      compiler->scalar_gs = true;
+
    nir_shader_compiler_options *nir_options =
       rzalloc(compiler, nir_shader_compiler_options);
    nir_options->native_integers = true;