From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jul 2019 09:54:05 +0000 (+0100)
Subject: add FPADD stack documentation
X-Git-Tag: ls180-24jan2020~826
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55e56bd7eb741136b60a56b3ff11470410862b81;p=ieee754fpu.git

add FPADD stack documentation
---

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 9a7820f7..9c51c3ca 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -1,6 +1,36 @@
-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
+"""IEEE Floating Point Adder Pipeline
+
+Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=75
+
+Stack looks like this:
+
+* scnorm    - FPMulSpecialCasesDeNorm
+* addalign  - FPAddAlignSingleAdd
+* normpack  - FPNormToPack
+
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+------                             ospec FPSCData
+
+                StageChain: FPMULSpecialCasesMod,
+                            FPAddDeNormMod
+                            FPAlignModSingle
+
+addalign  - FPAddAlignSingleAdd    ispec FPSCData
+--------                           ospec FPAddStage1Data
+
+                StageChain: FPAddAlignSingleMod
+                            FPAddStage0Mod
+                            FPAddStage1Mod
+
+normpack  - FPNormToPack           ispec FPAddStage1Data
+--------                           ospec FPPackData
+
+                StageChain: Norm1ModSingle,
+                            RoundMod,
+                            CorrectionsMod,
+                            PackMod
+
+"""
 
 from nmigen import Module
 from nmigen.cli import main, verilog