From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 19:42:44 +0000 (+0100) Subject: clarify X-Git-Tag: opf_rfc_ls005_v1~486 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55ef60c52daa5bb44ed6dc3e41c7bfaa529acbdf;p=libreriscv.git clarify --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index a42df4b2c..90dc372be 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -124,7 +124,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures. # Simple-V Architectural Resources * No new Interrupt types are required. - (**No modifications to existing Power ISA are required either**). + (**No modifications to existing Power ISA opcodes are required either**). * GPR FPR and CR Field Register extend to 128. A future version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx] * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)