From: enjoy-digital <florent@enjoy-digital.fr>
Date: Mon, 19 Feb 2018 11:27:25 +0000 (+0100)
Subject: Merge pull request #60 from q3k/for-upstream/top-level-module-selection
X-Git-Tag: 24jan2021_ls180~1742
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55fc9d2d6bdc343f569ded3ab3415f260f2a96ab;p=litex.git

Merge pull request #60 from q3k/for-upstream/top-level-module-selection

Top module selection (for Verilator and Diamond)
---

55fc9d2d6bdc343f569ded3ab3415f260f2a96ab
diff --cc litex/build/sim/core/Makefile
index 782ac46b,8ccb4ff0..733ea531
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@@ -24,8 -24,9 +24,9 @@@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.
  
  .PHONY: sim
  sim: mkdir $(OBJS_SIM)
 -	verilator -Wno-fatal -O3 --cc dut.v --exe \
 +	verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
  		$(SRCS_SIM_CPP) $(OBJS_SIM) \
+ 		--top-module dut \
  		-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
  		-LDFLAGS "$(LDFLAGS)" \
  		-trace $(INC_DIR)