From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 23 Feb 2019 18:15:05 +0000 (-0800)
Subject: moving CamEntry to src
X-Git-Tag: div_pipeline~2385
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=55ff914b364d7b58bdc528599247a623839c6906;p=soc.git

moving CamEntry to src
---

diff --git a/TLB/CamEntry.py b/TLB/CamEntry.py
deleted file mode 100644
index 5b4cb2fb..00000000
--- a/TLB/CamEntry.py
+++ /dev/null
@@ -1,44 +0,0 @@
-from nmigen import Module, Signal
-
-# Content Addressable Memory (CAM) Entry
-# The purpose of this module is to represent an entry within a CAM.
-# This module when given a read command will compare  the given key
-# and output whether a match was found or not. When given a write
-# command it will write the given key and data into internal registers.
-class CamEntry:
-    
-    # Arguments:
-    #  key_size: (bit count) The size of the key 
-    #  data_size: (bit count) The size of the data 
-    def __init__(self, key_size, data_size):
-        # Internal
-        self.key = Signal(key_size)
-        
-        # Input
-        self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reserve
-        self.key_in = Signal(key_size) # Reference key for the CAM
-        self.data_in = Signal(data_size) # Data input when writing
-        
-        # Output
-        self.match = Signal(1) # Result of the internal/input key comparison
-        self.data = Signal(data_size)
-        
-        
-    def get_fragment(self, platform=None):
-        m = Module()
-        with m.Switch(self.command):
-            with m.Case("01"):
-                with m.If(self.key_in == self.key):
-                    m.d.sync += self.match.eq(1)
-                with m.Else():
-                    m.d.sync += self.match.eq(0)
-            with m.Case("10"):
-                m.d.sync += [
-                    self.key.eq(self.key_in),
-                    self.data.eq(self.data_in),
-                    self.match.eq(0)
-                ] 
-            with m.Case():
-                m.d.sync += self.match.eq(0)
-        
-        return m
diff --git a/TLB/src/CamEntry.py b/TLB/src/CamEntry.py
new file mode 100644
index 00000000..5b4cb2fb
--- /dev/null
+++ b/TLB/src/CamEntry.py
@@ -0,0 +1,44 @@
+from nmigen import Module, Signal
+
+# Content Addressable Memory (CAM) Entry
+# The purpose of this module is to represent an entry within a CAM.
+# This module when given a read command will compare  the given key
+# and output whether a match was found or not. When given a write
+# command it will write the given key and data into internal registers.
+class CamEntry:
+    
+    # Arguments:
+    #  key_size: (bit count) The size of the key 
+    #  data_size: (bit count) The size of the data 
+    def __init__(self, key_size, data_size):
+        # Internal
+        self.key = Signal(key_size)
+        
+        # Input
+        self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reserve
+        self.key_in = Signal(key_size) # Reference key for the CAM
+        self.data_in = Signal(data_size) # Data input when writing
+        
+        # Output
+        self.match = Signal(1) # Result of the internal/input key comparison
+        self.data = Signal(data_size)
+        
+        
+    def get_fragment(self, platform=None):
+        m = Module()
+        with m.Switch(self.command):
+            with m.Case("01"):
+                with m.If(self.key_in == self.key):
+                    m.d.sync += self.match.eq(1)
+                with m.Else():
+                    m.d.sync += self.match.eq(0)
+            with m.Case("10"):
+                m.d.sync += [
+                    self.key.eq(self.key_in),
+                    self.data.eq(self.data_in),
+                    self.match.eq(0)
+                ] 
+            with m.Case():
+                m.d.sync += self.match.eq(0)
+        
+        return m