From: Luke Kenneth Casson Leighton Date: Wed, 10 Jun 2020 16:04:33 +0000 (+0100) Subject: expand LenExpand to 4 bits in order to cover 1/2/4/8 (0b1000) X-Git-Tag: div_pipeline~413 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56014813b9b1923d8111017e6e109a450bd6edb0;p=soc.git expand LenExpand to 4 bits in order to cover 1/2/4/8 (0b1000) --- diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index f743e6b9..5e4000c5 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -358,7 +358,7 @@ class L0CacheBuffer(Elaboratable): m.submodules.ldpick = ldpick = PriorityEncoder(self.n_units) m.submodules.stpick = stpick = PriorityEncoder(self.n_units) - m.submodules.lenexp = lenexp = LenExpand(3, 8) + m.submodules.lenexp = lenexp = LenExpand(4, 8) lds = Signal(self.n_units, reset_less=True) sts = Signal(self.n_units, reset_less=True)