From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 18:53:21 +0000 (+0200)
Subject: Simplified $__arraymul techmap rule
X-Git-Tag: yosys-0.4~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5602cbde9f9f86197511036d8873c0f8fb1ca5d7;p=yosys.git

Simplified $__arraymul techmap rule
---

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index e1d5bd82f..7a4f6b272 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -502,15 +502,21 @@ module \$__arraymul (A, B, Y);
 	input [WIDTH-1:0] A, B;
 	output [WIDTH-1:0] Y;
 
-	wire [WIDTH*WIDTH-1:0] partials;
+	wire [1023:0] _TECHMAP_DO_ = "proc;;";
 
-	genvar i;
-	assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
-	generate for (i = 1; i < WIDTH; i = i+1) begin:gen
-		assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
-	end endgenerate
+	integer i;
+	reg [WIDTH-1:0] x, y;
+
+	always @* begin
+		x = B;
+		y = A[0] ? x : 0;
+		for (i = 1; i < WIDTH; i = i+1) begin
+			x = {x[WIDTH-2:0], 1'b0};
+			y = y + (A[i] ? x : 0);
+		end
+	end
 
-	assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
+	assign Y = y;
 endmodule
 
 module \$mul (A, B, Y);