From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 05:12:55 +0000 (-0700)
Subject: More meaningful error message
X-Git-Tag: working-ls180~1237^2~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5605002d8a583409a56d1187460de1f4a03d8454;p=yosys.git

More meaningful error message
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index c8272153d..6356d4fbf 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -118,6 +118,8 @@ void handle_loops(RTLIL::Design *design)
 			auto jt = box_module->attributes.find("\\abc_scc_break");
 			if (jt != box_module->attributes.end()) {
 				auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string()));
+				if (it == cell->connections_.end())
+					log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module));
 				log_assert(it != cell->connections_.end());
 				auto &c = *it;
 				SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string()));