From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 11:13:26 +0000 (+0100)
Subject: code-munging
X-Git-Tag: div_pipeline~1209
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=560c2f9e7552f6dc46f8f119a20968cf60a013c0;p=soc.git

code-munging
---

diff --git a/src/soc/countzero/countzero.py b/src/soc/countzero/countzero.py
index ae0a30df..7826d947 100644
--- a/src/soc/countzero/countzero.py
+++ b/src/soc/countzero/countzero.py
@@ -66,7 +66,7 @@ class ZeroCounter(Elaboratable):
         r = IntermediateResult()
         r_in = IntermediateResult()
 
-        m.d.comb += r.eq(r_in)# make the module entirely combinatorial for now
+        m.d.comb += r.eq(r_in) # make the module entirely combinatorial for now
 
         v = IntermediateResult()
         y = Signal(4, reset_less=True)
@@ -129,7 +129,7 @@ class ZeroCounter(Elaboratable):
             m.d.comb += o[5:7].eq(Cat(r.is_32bit, ~r.is_32bit))
         with m.Elif(r.count_right):
             # return (63 - sel), trimmed to 5 bits in 32-bit mode
-            m.d.comb += o.eq(Cat(~sel[0:5], (~sel[5] & ~r.is_32bit)))
+            m.d.comb += o.eq(Cat(~sel[0:5], ~(sel[5] | r.is_32bit)))
         with m.Else():
             m.d.comb += o.eq(sel)