From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 21:35:19 +0000 (+0100)
Subject: add sc back in
X-Git-Tag: div_pipeline~162^2~75
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5617a3beff54b541daafce6aaf5d4cc1abc2105e;p=soc.git

add sc back in
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index fa29c94d..0737ced8 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -193,13 +193,13 @@ class TrapMainStage(PipeModBase):
                 msr_check_pr(m, msr_o.data)
                 comb += msr_o.ok.eq(1)
 
-            # TODO (later) - add OP_SC
-            #with m.Case(InternalOp.OP_SC):
-            #    # TODO: scv must generate illegal instruction.  this is
-            #    # the decoder's job, not ours, here.
-            #
-            #    # jump to the trap address, return at cia+4
-            #    self.trap(m, 0xc00, cia_i+4)
+            # OP_SC
+            with m.Case(InternalOp.OP_SC):
+                # TODO: scv must generate illegal instruction.  this is
+                # the decoder's job, not ours, here.
+
+                # jump to the trap address, return at cia+4
+                self.trap(m, 0xc00, cia_i+4)
 
             # TODO (later)
             #with m.Case(InternalOp.OP_ADDPCIS):