From: Andrew Waterman Date: Mon, 29 Feb 2016 07:51:53 +0000 (-0800) Subject: WIP on priv spec v1.9 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5618582e2fdbece0c3125c430fc660faea479b62;p=riscv-isa-sim.git WIP on priv spec v1.9 --- diff --git a/riscv/encoding.h b/riscv/encoding.h index 411a7af..1127234 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -647,11 +647,6 @@ #define CSR_SIP 0x144 #define CSR_SPTBR 0x180 #define CSR_SASID 0x181 -#define CSR_CYCLEW 0x900 -#define CSR_TIMEW 0x901 -#define CSR_INSTRETW 0x902 -#define CSR_STIME 0xd01 -#define CSR_STIMEW 0xa01 #define CSR_MSTATUS 0x300 #define CSR_MEDELEG 0x302 #define CSR_MIDELEG 0x303 @@ -664,26 +659,25 @@ #define CSR_MBADADDR 0x343 #define CSR_MIP 0x344 #define CSR_MIPI 0x345 -#define CSR_MTIME 0x701 -#define CSR_MISA 0xf00 -#define CSR_MVENDORID 0xf01 -#define CSR_MARCHID 0xf02 -#define CSR_MIMPID 0xf03 -#define CSR_MCFGADDR 0xf04 -#define CSR_MHARTID 0xf10 +#define CSR_MCYCLE 0xf00 +#define CSR_MTIME 0xf01 +#define CSR_MINSTRET 0xf02 +#define CSR_MISA 0xf10 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MCFGADDR 0xf14 +#define CSR_MHARTID 0xf15 #define CSR_MTOHOST 0x7c0 #define CSR_MFROMHOST 0x7c1 #define CSR_MRESET 0x7c2 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 -#define CSR_CYCLEHW 0x980 -#define CSR_TIMEHW 0x981 -#define CSR_INSTRETHW 0x982 -#define CSR_STIMEH 0xd81 -#define CSR_STIMEHW 0xa81 #define CSR_MTIMECMPH 0x361 -#define CSR_MTIMEH 0x781 +#define CSR_MCYCLEH 0xf80 +#define CSR_MTIMEH 0xf81 +#define CSR_MINSTRETH 0xf82 #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 @@ -958,11 +952,6 @@ DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(sptbr, CSR_SPTBR) DECLARE_CSR(sasid, CSR_SASID) -DECLARE_CSR(cyclew, CSR_CYCLEW) -DECLARE_CSR(timew, CSR_TIMEW) -DECLARE_CSR(instretw, CSR_INSTRETW) -DECLARE_CSR(stime, CSR_STIME) -DECLARE_CSR(stimew, CSR_STIMEW) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) @@ -975,7 +964,9 @@ DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mbadaddr, CSR_MBADADDR) DECLARE_CSR(mip, CSR_MIP) DECLARE_CSR(mipi, CSR_MIPI) +DECLARE_CSR(mcycle, CSR_MCYCLE) DECLARE_CSR(mtime, CSR_MTIME) +DECLARE_CSR(minstret, CSR_MINSTRET) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) @@ -988,13 +979,10 @@ DECLARE_CSR(mreset, CSR_MRESET) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(cyclehw, CSR_CYCLEHW) -DECLARE_CSR(timehw, CSR_TIMEHW) -DECLARE_CSR(instrethw, CSR_INSTRETHW) -DECLARE_CSR(stimeh, CSR_STIMEH) -DECLARE_CSR(stimehw, CSR_STIMEHW) DECLARE_CSR(mtimecmph, CSR_MTIMECMPH) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(mtimeh, CSR_MTIMEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) diff --git a/riscv/processor.cc b/riscv/processor.cc index f60d00a..34735f9 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -282,38 +282,6 @@ void processor_t::set_csr(int which, reg_t val) state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT; state.frm = (val & FSR_RD) >> FSR_RD_SHIFT; break; - case CSR_MTIME: - case CSR_STIMEW: - // this implementation ignores writes to MTIME - break; - case CSR_MTIMEH: - case CSR_STIMEHW: - // this implementation ignores writes to MTIME - break; - case CSR_TIMEW: - val -= sim->rtc; - if (xlen == 32) - state.sutime_delta = val | (state.sutime_delta >> 32 << 32); - else - state.sutime_delta = val; - break; - case CSR_TIMEHW: - val = ((val << 32) - sim->rtc) >> 32; - state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta; - break; - case CSR_CYCLEW: - case CSR_INSTRETW: - val -= state.minstret; - if (xlen == 32) - state.suinstret_delta = val | (state.suinstret_delta >> 32 << 32); - else - state.suinstret_delta = val; - break; - case CSR_CYCLEHW: - case CSR_INSTRETHW: - val = ((val << 32) - state.minstret) >> 32; - state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta; - break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM)) @@ -424,34 +392,12 @@ reg_t processor_t::get_csr(int which) if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); - case CSR_MTIME: - case CSR_STIME: - case CSR_STIMEW: - return sim->rtc; - case CSR_MTIMEH: - case CSR_STIMEH: - case CSR_STIMEHW: - return sim->rtc >> 32; - case CSR_TIME: - case CSR_TIMEW: - return sim->rtc + state.sutime_delta; - case CSR_CYCLE: - case CSR_CYCLEW: - case CSR_INSTRET: - case CSR_INSTRETW: - return state.minstret + state.suinstret_delta; - case CSR_TIMEH: - case CSR_TIMEHW: - if (xlen == 64) - break; - return (sim->rtc + state.sutime_delta) >> 32; - case CSR_CYCLEH: - case CSR_INSTRETH: - case CSR_CYCLEHW: - case CSR_INSTRETHW: - if (xlen == 64) - break; - return (state.minstret + state.suinstret_delta) >> 32; + case CSR_MTIME: return sim->rtc; + case CSR_MCYCLE: return state.minstret; + case CSR_MINSTRET: return state.minstret; + case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32; + case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32; + case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_PUM; diff --git a/riscv/processor.h b/riscv/processor.h index b01d5bf..7d71b31 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -59,8 +59,6 @@ struct state_t reg_t stvec; reg_t sptbr; reg_t scause; - reg_t sutime_delta; - reg_t suinstret_delta; reg_t tohost; reg_t fromhost; uint32_t fflags;