From: lkcl <lkcl@web>
Date: Fri, 9 Mar 2018 13:35:58 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5790
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56192aa902e1d7acbc42c183bd4e217ea07aac31;p=libreriscv.git

---

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 6748b9f8e..2434f3ef6 100644
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -4,4 +4,4 @@ See also [[AXI]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
-* <https://github.com/albertxie/iverilog-tutorial.git>
+* <https://github.com/qermit/WishboneAXI>