From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 11:16:20 +0000 (+0100)
Subject: dynamically specify wishbone layout (no longer hardcoded addr/data)
X-Git-Tag: div_pipeline~268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=562136e4592def55c2e404e3336ae3c55f0e3a94;p=soc.git

dynamically specify wishbone layout (no longer hardcoded addr/data)
---

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 396ee488..c74f6042 100644
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -12,7 +12,7 @@ __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit",
 
 class LoadStoreUnitInterface:
     def __init__(self, addr_wid=32, mask_wid=4, data_wid=32):
-        self.dbus = Record(wishbone_layout)
+        self.dbus = Record(mk_wb_layout(addr_wid, mask_wid, data_wid))
         self.mask_wid = mask_wid
         self.addr_wid = addr_wid
         self.data_wid = data_wid
diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py
index e26e072c..fa6bca3e 100644
--- a/src/soc/minerva/wishbone.py
+++ b/src/soc/minerva/wishbone.py
@@ -1,9 +1,10 @@
 from nmigen import Array, Elaboratable, Module, Record, Signal
 from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
 from nmigen.lib.coding import PriorityEncoder
+from nmigen.utils import log2_int
 
 
-__all__ = ["Cycle", "wishbone_layout", "WishboneArbiter"]
+__all__ = ["Cycle", "wishbone_layout", "make_wb_layout", "WishboneArbiter"]
 
 
 class Cycle:
@@ -13,19 +14,25 @@ class Cycle:
     END       = 7
 
 
-wishbone_layout = [
-    ("adr",   30, DIR_FANOUT),
-    ("dat_w", 32, DIR_FANOUT),
-    ("dat_r", 32, DIR_FANIN),
-    ("sel",    4, DIR_FANOUT),
-    ("cyc",    1, DIR_FANOUT),
-    ("stb",    1, DIR_FANOUT),
-    ("ack",    1, DIR_FANIN),
-    ("we",     1, DIR_FANOUT),
-    ("cti",    3, DIR_FANOUT),
-    ("bte",    2, DIR_FANOUT),
-    ("err",    1, DIR_FANIN)
-]
+def make_wb_layout(addr_wid, mask_wid, data_wid):
+    adr_lsbs = log2_int_mask_wid)        # LSBs of addr covered by mask
+    badwid = addr_wid-log2_int(adr_lsbs) # MSBs (not covered by mask)
+
+    return [
+    ("adr",   badwid  , DIR_FANOUT),
+    ("dat_w", data_wid, DIR_FANOUT),
+    ("dat_r", data_wid, DIR_FANIN),
+    ("sel",   mask_wid, DIR_FANOUT),
+    ("cyc",           1, DIR_FANOUT),
+    ("stb",           1, DIR_FANOUT),
+    ("ack",           1, DIR_FANIN),
+    ("we",            1, DIR_FANOUT),
+    ("cti",           3, DIR_FANOUT),
+    ("bte",           2, DIR_FANOUT),
+    ("err",           1, DIR_FANIN)
+    ]
+
+wishbone_layout = make_wb_layout(32, 4, 32)
 
 
 class WishboneArbiter(Elaboratable):